Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/10101
標題: 低介電及高可靠度薄膜材料應用於內連導線之研究
Studies on the Low-k Dielectric and High Reliability Thin Film Materials for Interconnects
作者: 魏伯州
Wei, Bor-Jou
關鍵字: High-density-plasma chemical vapor deposition (HDP-CVD)
高密度電漿化學氣相沉積 (HDP-CVD)
Fluorinat-ed-silicate-glass (FSG)
Plasma enhanced chemical vapor deposition (PE-CVD)
Di-ethoxymethylsiliane (DEMS)
Trimethylsilane (3MS)
Thin film resistor.
氟矽玻璃(FSG)
電漿輔助化學氣相沉積 (PE-CVD)
二乙氧基甲基矽烷 (DEMS)
三甲基矽甲烷 (3MS)
Thin 薄膜電阻器。
出版社: 材料科學與工程學系所
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摘要: 為了使IC產業繼續符合Moore’s law,在元件尺寸持續不斷縮小的情況下,多層金屬內連導線已經被運用來增加晶片上的積集度,但內連導線的時間延遲卻比整個元件的時間延遲來得更加嚴重。多層金屬內連導線是由金屬導線、層與層之間的介電層薄膜、金屬之間的介電層薄膜所組成。隨著元件尺寸縮減,後段金屬導線亦需跟隨著微型化且單一層導線而不敷使用,必須建構多層內導線才得以全部連結,除增加製造程序的複雜度外,與元件微型化不同的是,金屬導線傳輸的速度會隨著尺寸之縮短而更加遲緩,衍生所謂電阻-電容時間延遲(RC delay time)。在内連導線結構中,使用低介電常數材料是一可行且克服此問題的方法之一。 本論文是探討數個低介電常數和電阻器材料之性質及其在半導體製程整合和可靠度研究。主要研究的材料包括:氟矽玻璃(Fluorosilicate glass, FSG),以二乙氧基甲基矽烷(Diethoxymethylsiliane, DEMS)和三甲基矽甲烷(Trimethylsilane, 3MS)為反應前驅物的摻碳有機矽鹽玻璃(Carbon-doped organo-silicate glass, OSG) 等低介電常數和Ti/TiN 薄膜電阻器材料。 在HDP-CVD FSG薄膜製程中,加入N2條件下;由實驗結果顯示,Si-F的濃度增加,進而降低介電常數值並且增進間隙填充能力。此外,在半導體製程中,熱處理為不可避免的步驟,因此高熱阻抗也為低介電材料必要之條件。吾人發現N-FSG可改變沉積薄膜之結構,得到較佳的低介電材料性質亦可增加製程整合之穩定性。 在PECVD的製程條件下,較低之介電常數及較高之機械性質是同時被要求的,對於IC的速度和後段封裝而言。吾人發現利用二乙氧基甲基矽烷(Diethoxymethylsiliane, DEMS)來取代目前所用之反應前驅物三甲基矽甲(Trimethylsilane, 3MS);由實驗結果顯示,在薄膜的性質及實際的製程整合結構中,DEMS-based 的低介電質沉積膜有較優良之電性性質、機械強度及熱穩定性,以及在製程整合中之優越性。 以Ti/TiN薄膜為電阻器的電性和可靠性已經被研究。實驗結果證明以Ti/TiN薄膜為電阻器時具有良好的熱穩定性。經由電性量測和電流應力測試結果顯示,Ti層薄膜相較於TiN層薄膜具較低的電阻抗能力。此外,在電流應力測試後,主要失效機制是Joule-heating造成Ti/TiN薄膜電阻器晶粒成長和線路斷路。Ti和TiN薄膜其活化能分別為1.8和1.2eV。假設Ti/TiN薄膜電阻器操作溫度小於311oC下,其可靠度可確保在十年的操作期間Ti/TiN薄膜的電阻值不會發生變化。
In order to integrated circuit (IC) industry following Moore's law, for scal-ing downing the device the multilevel interconnect had used to increase the densities of circuits on a chip, interconnect delay is becoming predominant over device delay time. As the device dimensions continue to shrink, interconnect delay becomes a lim-iting factor for increasing circuit device speed. The multilevel interconnect basically consists of metal layers, inter-layer dielectric (ILD) and inter-metal dielectric (IMD). As the device dimensions continue to shrink, interconnect delay becomes a limiting factor for increasing circuit device speed. Since interconnect delay is the product of the resistance in metal interconnect and the capacitance between the metal lines, the minimization of the parasitic capacitance and the resistance in interconnect is required. Incorporation of low-dielectric-constant materials in multilevel interconnect can ef-fectively reduce parasitic capacitance, thus decreasing the transmission delay. In this study, several kinds of low dielectric constant and resistors materials are investigated, including fluorine-silicate-glass (FSG), carbon-doped organo-silicate glass using trimethylsilane (3MS) and diethoxymethylsilane (DEMS) as precursors, and Ti/TiN thin films. The effects of the low-k dielectric constant materials on the in-tegration issue are studied to evaluate the compatibility of low-k materials on semi-conductor process. Moreover, the reliability of Ti/TiN thin film resistors were demon-strated no wear out issue below 311oC. As N2 is added in the FSG films by high-density-plasma chemical vapor deposition (HDP-CVD) method, higher fluorine concentration, reduced dielectric constant and improved gap filling ability of the deposited films have been achieved. It is proposed that the improvement of stability is correlated with the reduction of unstable fluorine bonds in the N-FSG films. Furthermore, the thermal stability of the N-FSG films was also identified by Al wiring delamination check. After annealing, the blister was observed only in non-N2 FSG film with 5.5 % Si-F concentration, while no blisters or delamination were observed when N2 is introduced into the FSG process. Therefore, the N-FSG film, deposited by HDP-CVD, is a good candidate for interconnects dielectric application. Lower dielectric constant as well as higher mechanical strength of plasma en-hanced chemical vapor deposition (PE-CVD) low-k films is required for IC speed and package. Both low-k films deposited using 3MS and DEMS precursors have similar elemental composition, but different bonding structures, leading to different integra-tion results. DEMS-based low-k films have a lower dielectric constant, higher hard-ness, and higher chemical and thermal stability than 3MS-based low-k films. From the results of blanket films and four-level interconnect test devices, the DEMS-based films were found to have superior electrical performance than that of the 3MS-based films. Ti/TiN thin film resistors were characterized by making electrical and reliability measurements. The results demonstrate that the Ti/TiN thin film resistor has an ex-cellent thermal stability up to 350oC. Based on electrical measurement and stress, the Ti layer has a lower electrical resistance than the TiN layer. Furthermore, the main failure mechanism of the Ti/TiN thin film resistors is thermally activated by Joule-heating. The thermal activation energy for failure is determined to be 1.8 eV for the Ti layer and 1.2 eV for the TiN layer. Based on this result, Ti/TiN thin film resis-tors exhibit no significant change in resistance during a lifetime of ten years if their temperature remains below 311oC.
URI: http://hdl.handle.net/11455/10101
其他識別: U0005-0502201216400000
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0502201216400000
Appears in Collections:材料科學與工程學系

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