請用此 Handle URI 來引用此文件: http://hdl.handle.net/11455/10529
標題: Analysis of Warpage Issue in Flip-Chip Ball Grid Arrays
覆晶球柵陣列構裝之翹曲分析研究
作者: 蔡君聆
Tsai, Jyun-Ling
關鍵字: Shadow Moire
陰影疊紋法
Heatspreader adhesive
Pattern
Warpage
散熱片黏著膠
塗佈方式
翹曲量
出版社: 材料科學與工程學系所
引用: [1] R. Darveaux, I. Turlik, Lih-Tyng Hwang and A. Reisman, “Thermal Stress Analysis of a Multichip Package Design,” IEEE Electronic Components Conference, Vol.39, pp.668-671, 1989. [2] G. Kelly, C. Lyden, W. Lawton, J. Barrett, A. Saboui, H. Page and H. Peters, “The Importance of Molding Compound Cahemical Shrinkage in the Stress and Warpage Analysis of PQFPs,” IEEE Electronic Components and Technology Conference,Vol.45, pp.977-981, 1995. [3] Q. Yao and J. Qu, “Three-Dimensional Versus Two- Dimensional Finite Element Modeling of Flip-Chip Packages,” ASME Journal of Electronic Packaging, Vol.121, pp.196-201, 1999. [4] 嚴嘉進,“回焊溫度與滯留時間之變化對PBGA構裝體翹曲之影響”, 國立中山大學機械與機電工程研究所碩士論文,pp88-89,2001。 [5] 洪健雄、錢志回、蔡明郎、邱以泰,“半導體構裝體於不同溫濕保存環境下經IR-reflow 過程後翹曲現象之研究”,國立中山大學機械與機電工程研究所碩士論文,pp44-45,2000。 [6] 邱以泰、錢志回、蔡明郎、張志方,“全像干涉術應用於半導體構裝經IR-reflow 過程中在不同溫昇速率及停留溫高下翹曲之研究”,中華民國力學學會第二十四屆全國力學會議論文集,pp48-55,2000。 [7] 葉曉謙,“覆晶晶粒尺寸構裝之熱應力分析”,國立中山大學機械工程學系研究所所碩士論文,pp65-66, 2000。 [8] Y. Freedman and C. Eason, “The instruction of warpage improvement guidelines for BGA performance within SMT temperature profile,” IEEE Electronic Packaging Technology, Vol.8, pp1-5, 2007. [9] L. CheeKan and L. WeiKeat, “Study of Dynamic warpage of flip chip Package under Temperature Reflow,” IEEE Electronic Manufacturing and Technology, Vol.31, pp185-190, 2007. [10] W. Y Y and P. Hassell, “Measurement of Thermally Induced Deformation of a BGA Using Phase-Stepping Shadow Moire,” IEEE Electronic Packaging Technology Conference, Vol.1, pp283-289, 1997. [11] M. R. Stiteler and C. Ume, “System for Real Time Measurement of Thermally Induced PWB/PWA Warpage,” ASME Journal of Electronic Packaging, Vol.119, pp1-7, 1997. [12] 黃昭彰,“相移陰影疊紋量測系統在半導體暨電子構裝之應用,”, 國立台灣大學應用力學研究所碩士論文,pp45-46,1998。 [13] 高迺澔,“塑封球柵陣列與覆晶構裝之應力量測與分析,”,國立台灣大學應用力學研究所碩士論文,pp62-63,1999。 [14] G. Phil and B. Tozer, “Application of Shadow Moire Technique to Board Level Manufacturing Technologies,” IEEE Electronic components Technology Conference, Vol.152, pp1816-1820, 2006. [15] 吳俊生,“以雲紋干涉術探討機械加工對於電子封裝體熱行為之影響,”, 國立清華大學動力機械工程學系碩士論文,pp5,2001。 [16] 郭昱綸,“覆晶球柵陣列電子封裝體在溫度循環下的熱應力與熱應變分析,”國立中山大學機械與機電工程學系碩士論文,pp16-19,2003。 [17] Operation Manual, “TherMoire System, Model PS400,”2008. [18] JEDEC Standard No. 22B112, “High Temperature Package Warpage Measurement Methodology,” pp4-5, 2005.
摘要: 本文乃利用陰影疊紋法來量測散熱片型覆晶球柵陣列構裝體,搭配不同散熱片黏著膠與其不同的黏著膠塗佈方式來驗證,在預設的溫度條件下構裝體翹曲表現,希望能藉此提供較佳的構裝體抗變形強度的材料組合,使其受熱應力破壞降到最低。 在散熱片黏著膠材料性質比較方面,高玻璃轉換溫度和低熱膨脹係數的散熱片黏著膠具有較佳的抗構裝體翹曲變形行為。相同的散熱片黏著膠塗佈形狀(4L-type 或 U sharp)在不同的散熱片黏著膠材料(X type 或 M type)的構裝體,其在最高溫260℃時的翹曲量差異分別為0.5 mils 與1.2 mils。所以由此實驗結果顯示,在選擇散熱片黏著膠材料時可以盡量朝這個方向去做選擇。另外,在散熱片黏著膠塗佈形狀的比較方面,以U shape與4L+dot黏著膠塗佈形狀的翹曲曲線表現最好,在最高溫260℃時的翹曲量分別為1.8 mils 和1.5 mils。在考量構裝體整體的黏著膠塗佈覆蓋面積時,可朝在構裝體的四個角落皆有塗佈黏著膠的方向去做選擇。
The thesis seeks to discuss in detail the best material and adhesive dispense matrix combination for reducing the thermal stress (package warpage) effect on a flip chip package at reflow temperature conditions. In this study, the Shadow Moiré Method was utilized to simulate and characterize the warpage performance of a flip chip package on varying reflow temperatures. In regards to the adhesive material properties for the heatspreader, the high glass-transition temperatures (Tg) and low coefficient of thermal expansion (CTE) characteristics show the better warpage performance. In the case of the flip chip package with similar heatspreader adhesive material (X type or M type) but of different type of heatspreader adhesive pattern (4L-type or U shape), the warpage deviations at peak temperature of 260℃ are 0.5 mils and 1.2 mils. This gives the criteria of material properties for choosing the suitable adhesive material. As regarding the heatspreader adhesive dispense pattern, the “four-line + dot shape” shows better results than the “U shape” adhesive pattern, where the warpage performance at peak temperature 260℃ were 1.8 mils and 1.5 mils, respectively. These indicate that the better adhesive pattern would further serve to control the flip chip package warpage.
URI: http://hdl.handle.net/11455/10529
其他識別: U0005-2407200719115300
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2407200719115300
顯示於類別:材料科學與工程學系

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