Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/11412
標題: 淺溝渠製程改善快閃記憶體可靠度之研究
Study of Shallow Trench Isolation Processes to Improve the Reliability on Flash Memory
作者: 張明豐
Chang, Ming-Feng
關鍵字: 快閃記憶體
flash memory
可靠度
淺溝渠製程
reliability
shallow trench isolation
出版社: 材料科學與工程學系所
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Aritome “A self-aligned STI process integration for low cost and highly reliable 1Gbit flash memories “ VLSI Technology, Digest of Technical Papers. 1998 Symposium on, p 102 – 103, 1998 [15]Ching-Yuan Ho, Chun-Hsing Shih ”Edge encroachments and suppression of tunnel oxide in flash memory cells,” IEEE Electron Device Letters, vol. 29, no. 10, October, 2008 [16]Jongoh Kim,Taewoo Kim, Jaebeom Park, Woojin Kim, Byungseop Hong, and Gyuhan Yoon“A Shallow Trench Isolation Using Nitric Oxide(NO)-Annealed Wall Oxide to Suppress Inverse Narrow Width Effect. ” IEEE Electron Device Letters, vol. 21. no. 12, 2000 [17]Karnett, M.; Qian, S.; Solis, R.; Tao, X.; Black, A.; Boonsanguan, S.; Liu, A., ”The influence of processing conditions on data retention behavior in a deep submicron NVM process” IEEEI/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, Page(s): 118 – 124, 2003 [18]A. Goda, W. Moriyama, H. Hazama, H. Iizuka, K. Shimizu, S. Aritome, R.Shirota, “A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories,” IEDM Tech. Dig., p. 771-774, 2000 [19]Z. Liu, S. Fujieda, F. Hayash, M. Shimizu, M. Nakata, H. Ishigaki, M. Wilde, K. Fukutani, “Influence of Hydrogen Permeability of Liner Nitride Film on Program/Erase Endurance of Split-Gate Type Flash EEPROMS,” IEEE proc. of IRPS, p. 190-196, 2007 [20]J. Kim, J. D. Choi, W. C. Shin, D. J. Kim, H. S. Kim, K. M. Mang, S. T. Ahn, O. H. Kwon, “Scaling down of tunnel oxynitride in NAND flash memory: oxynitride selection and reliabilities,” IEEE proc. of IRPS, p. 12-16, 1997 [21]Y.M. Park, J.S. Lee, M. Kim, , M.K. Cho, K. Kim, J.I. Han, D.W. Kwon, W.K. Lee, Y.H. Song, K.D. Suh,“The mechanical stress effects on data retention reliability of NOR flash memory,” IEDM Tech. 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摘要: 快閃記憶體(Flash Memory)技術發展已有20多年餘,其浮動閘極(Floating Gate)作為儲存區的快閃記憶體不斷的增進已經來到20奈米的世代,由於快閃記憶體屬於非揮發性記憶體,在製程不斷微縮之下其可靠度為一項嚴峻的考驗,因此於製程技術的改善來確保其可靠度之表現。 對於可靠度的製程改善已有許多期刊文獻發表,包括製程中電漿誘導之損傷(Plasma Induce Damage):其相關製程有後段介電層氧化物堆疊及金屬線蝕刻等製程改善、氫離子貫穿至穿隧氧化層(Hydrogen Penetrate Tunnel Oxide):其閘極後的氮化矽製程(spacer NIT/barrier NIT)改善以減少氫離子之貫穿、機械應力(Mechanical Stress):包括淺溝渠側壁氧化矽(STI Liner Oxide)及其閘極後的氮化矽製程(Spacer NIT/Barrier NIT)、穿隧氧化層完整度(Tunnel Oxide Integrity):包括淺溝渠蝕刻、淺溝渠側壁氧化矽(STI Liner Oxide)及穿隧氧化層(Tunnel Oxide)完整度。 本篇論文所探討研究的技術是120奈米NAND型快閃記憶體,探討穿隧氧化層完整度(Tunnel oxide integrity),利用淺溝渠隔離(Shallow Trench Isolation, STI)相關製程改善快閃記憶體可靠度之研究,其中包括淺溝渠側壁氧化層厚度的改善、淺溝渠側壁氧化層後增加額外的熱處理,淺溝渠氧化層沉積的方法更改等方式作為研究,利用這些製程的變更及改善來探討其對可靠度的影響,其中以淺溝渠氧化層沉積的方法更改對10萬次寫入(Program)、擦拭(Erase)後的起始電壓(Vt)變化量影響最小,擦拭電壓變化量由先前的3.88V改善至2.35V,並確保經10萬次寫入、擦拭後資料讀取之正確。
Flash Memory Technology has been developed over 20 years, and advance 20nm node floating gate structural flash is main stream on non-volatile memory market. And it faces reliability failure on process critical dimension shrinkage, therefore, it is important to improve process to ensure the reliability performance. Many papers of process improvement on reliability respect already disclosed in semiconductor engineering journals, including plasma induce damage; hydrogen penetrate to influence tunnel oxide quality; mechanical stress; tunnel oxide integrity and etc. these improvement research is on going. The technology of this paper was to focus on 120nm NAND type flash process technology. To investigate tunnel oxide integrity and to use shallow trench isolation related processes to improve the reliability, the experiments included additional N2 treatment after shallow trench isolation liner HTO(high temp. oxidation) oxide deposition; shallow trench isolation liner HTO(high temp. oxidation) oxide thickness split and different shallow trench isolation high density plasma oxide(STI HDP oxide) deposition method. Base on these experiments to check 100k cycling erase threshold voltage(Vte) difference, the minor erase threshold voltage(Vte) push up after 100k cycling was to change shallow trench isolation oxide deposition method. It was improved from 3.08V to 2.35V and it can judge the correct data after 100k cycling.
URI: http://hdl.handle.net/11455/11412
其他識別: U0005-2910201215485300
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2910201215485300
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