Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/17106
DC FieldValueLanguage
dc.contributor孫允武zh_TW
dc.contributorYuen-Wuu Suenen_US
dc.contributor裴靜偉zh_TW
dc.contributor李敏鴻zh_TW
dc.contributor李昌駿zh_TW
dc.contributor許博欽zh_TW
dc.contributorZingway Peien_US
dc.contributorMin-Hung Leeen_US
dc.contributorChang-Chun Leeen_US
dc.contributorB.-C. Hsuen_US
dc.contributor.advisor林中一zh_TW
dc.contributor.advisorChung-Yi Linen_US
dc.contributor.author廖淑慧zh_TW
dc.contributor.authorLiao, Shu-Huien_US
dc.contributor.other中興大學zh_TW
dc.date2009zh_TW
dc.date.accessioned2014-06-06T06:58:06Z-
dc.date.available2014-06-06T06:58:06Z-
dc.identifierU0005-2404200800314200zh_TW
dc.identifier.citationLIST OF REFERENCES CHAPTER 1 [1] K. Derbyshire, “Strain Engineering: Helping Transistors Scale Beyond 90 nm,” Semiconductor Manufacturing Magazine, vol. 6, 2005. [2] L. Collins, “Silicon Takes the Strain,” IEE Review, vol. 49, p. 46-49(2003). [3] Gamble HS. “Variants on bonded SOI for advanced ICs,” Electrochemical Soc. Proc., p.1-12(2001). [4] Plouchart J-O. “SOI nano-technology for high-performance system on-chip applications,” Proc IEEE Int SOI Conf., p. 1-4(2003). [5] Cai J, Ajmera A, Ouyang C, Oldiges P, Steigerwalt M, Stein K, et al. “Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI,” Tech Dig Symp VLSI Technol, p. 172-173(2002). [6] Q. Ouyang, J. Cai, P. Oldiges and J. Johnson, “A simulation study of thin SOI bipolar transistors with fully or partially depleted collector,” IEEE Proc. BCTM., p. 28-31(2002). CHAPTER 2 [1] K. Eberl, K. Brunner, and W. Winter, "Pseudomorphic Si1-yCy and Si1-x-yGexCy alloys on Si,” Thin Solid Films, vol. 294, p.98-104(1997). [2] M. Ershov and V. Ryzhii, "Monte Carlo study of electron transport in strained silicon-carbon alloy,” J. Appl. Phys., vol.76, p.1924-1926 (1994). [3] P. Dollfus et al., "Monte Carlo study of Sub-0.1μm Si0.97C0.03/Si MODFET: Electron Transport and Device Performance,” IEEE Trans. Electron Dev. vol.47 p.1247-1250 (2000). [4] K. Rim, T. O. Mitchell, J. L. Hoyt, G. Fountain, and J. F. Gibbons,” Eptaxy and applications of Si-based heterostructures,” Mat. Res. Soc. Symp. Proc. vol. 533, p. 43-48 (1998). [5] E. Quinones, S. K. Ray, K. C. Liu, and S. Banerjee, "Enhanced Mobility PMOSFET's Using Tensile-Strained Si1-yCy Layers,” IEEE Electron Device Lett. vol. 20, p.338-340 (1999). [6] T. Ernst, F. Ducroquet, J.-M. Hartmann, O. Weber, V. Loup, R. Truche, A. M. Papon, P. Holliger, B. Previtali, A. Toffoli, J. L. Di Maria, and S. Deleonibus, "A New Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics,” Symposium on VLSI Technology Digest, p.51-52 (2003). [7] C. Jacoboni and P. Lugli, "The Monte Carlo method for the solution of charge transport in semiconductors with applications to covalent materials,” Rev. Mod. Phys. vol. 55, p. 645-705 (1983). [8] S. T. Chang, C. Y. Lin and C. W. Liu, "Energy band structure of strained Si1-xCx Alloys on Si (001) substrate,” J. Appl. Phys. vol. 92, p. 3717-3723 (2002). [9] F. M. Bufler, “Full band Monte Carlo Simulation of Electrons and Holes in Strained Si and SiGe,” Munich: Herbert Utz Verlag, (1998). (http://utzverlag.com) [10] J. W. Harrison and J. R. Hauser, "Alloy scattering in ternary III-V compounds,” Phys. Rev. B, vol.12, p. 5347-5350 (1976). [11] F. Nava et al., "ELECTRON EFFECTIVE MASSES AND LATTICE SCATTERING IN NATURAL DIAMOND,” Solid State Commun., vol. 33, p.475-477 (1980). [12] H. Brooks and C. Herring,”Scattering by ionized impurities in semiconductors. Physical Review, vol. 83, p. 879 (1951). [13] D. M. Caughey and R. E. Thomas,”Carrier mobilities in silicon empirically related to doping and field,” Proc. IEEE, vol. 55, p. 2192-2193 (1967). [14] W. R. Thurber, R. L. Mattis, Y. M. Liu, and J. J. Filliben,” Resistivity-Dopant Density Relationship for Phosphorus-Doped Silicon,” J. Electrochem. Soc. vol.127 p.1807 (1980). [15] A. B. Sproul, M. A. Green, and A. W. Stephens, “Accurate determination of minority carrier-and lattice scattering-mobility in silicon from photoconductance decay,” J. Appl. Phys. vol. 72, p. 4161-4171 (1992). [16] J. Dziewior and D. Silber,” Minority-carrier diffusion coefficients in highly doped solicon,” Appl. Phys. Lett. vol. 35, p. 170-172 (1979). [17] S. E. Swirhun, Y.-H. Kwark, and R. M. Swanson,“Measurement of electron lifetime and electron mobility, band-gap narrowing in heavily doped p-type silicon,” IEDM Tech. Dig., p. 24-27 (1986). [18] Y. Fu, K. J. Grahn, and M. Willander,“Valance Band Structure of GexSi1-x for Hole Transport Calculation,“ IEEE Trans. Electron Devices, vol.41, p.26-31 (1994). CHAPTER 3 [1] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson,” Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High (∼1.5 GPa) Channel Stress,” IEEE Electron Device Lett., vol.28, p.58 -61(2007). [2] Scott E. Thompson, Guangyu Sun, Youn Sung Choi, and Toshikazu Nishida, ” Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap, ” IEEE Tran. Electron Devices, vol. 53, p.1010 -1020(2006). [3] T.Ghani, et al., “A 90nm high volume manufacturing logic technology ... length strained silicon CMOS transistors,” IEDM Technical Digest, p. 978-981 (2003). [4] M.Yang, et al., "Hybrid-Orientation Technology (HOT): Opportunities and Challenges," IEEE Trans. Electron Devices, vol. 53, p.965-978 (2006). [5] H. Irie, K. Kita, K. Kyuno, and A. Toriwni, “In-plane mobility anisotropy and universality under uni-axial strains in N- and P-MOS inversion layers on (100), (110), and (111) Si,” IEDM Tech. Digest, p.225-228 (2004). [6] L. Shifren, X. Wang, P. Matagne, B. Obradovic, C. Auth, S. Cea, T. Ghani, J. He, T. Hoffman, R. Kotlyar, Z. Ma, K. Mistry, R. Nagisetty, R. Shaheed, M. Stettler, C. Weber, and M. D. Giles,“Drive current enhancement in p-type metal-oxide-semiconductor field-effect transistors under shear uniaxial stress,” Appl. Phys. Lett., vol. 85, p. 6188-6190 (2004). [7] A.Rahman, Mark S. Lundstrom, and Avik W. Ghosh,”Generalized effective-mass approach for n-type metal-oxide-semiconductor field-effect transistors on arbitrarily oriented wafers,” J. Appl. Phys., vol.97, p. 53702-1-53702-12 (2005). [8] K.Uchida, Tejas Krishnamohan, Krishna C. Saraswat, and Yoshio Nishi,” Physical Mechanisms of Electron Mobility Enhancement in Uniaxial Stressed MOSFETs and Impact of Uniaxial Stress Engineering in Ballistic Regime,” IEDM Technical Digest, p. 129-132 (2005). [9] G. Dresselhaus, A. F. Kip, and C. Kittel,”Cyclotron Resonance of Electrons and Holes in Silicon and Germanium Cryatals,” Phys. Rev. B, vol. 98, p. 368-384 (1955). [10] G. L. Bir and G. E. Pikus, “Symmetry and Straine-Induced Effects in Semiconductors,” Wiley, New York, p.321 (1974). [11] M. M. Rieger and P. Vogl, “Electronic-band parameters in strained Si1-xGex alloys on Si1-yGey substrates,” Phys. Rev. B, vol.48, p.14276-14287 (1993). [12] F. Stern and W. E. Howard,”Properties of Semiconductor Surface Inversion Layers in the Electric Quantum Limit,” Phys. Rev., vol. 163, p.816-835 (1967). [13] J. J. Wortman and R. A. Evans,”Young''s Modulus, Shear Modulus, and Poisson''s Ratio in Silicon and Germanium,” J. Appl. Phys. vol. 36, 153 (1965). [14] R. Kotlyar,M. D. Giles, P.Matagne, B. Obradovic, L. Shifren, M. Stettler, and E. Wang,”Inversion Mobility and Gate Leakage in High-Metal Gate MOSFETs,” IEDM Tech. Dig., p.301-394 (2004). [15] K. Natori,”Ballistic metal-oxide-semiconductor field effect transistor,” Journal of Applied Physics, vol. 76, p.4879-4890 (1994) [16] S. Takagi, “Re-examination of subband structure engineering in ultra-short channel MOSFET's under ballistic carrier transport,” Symp. VLSI Tech., p. 115-116 (2003). [17] M. De Michielis, D. Esseni, and F. Driussi,” Analytical Models for the Insight Into the Use of Alternative Channel Materials in Ballistic nano-MOSFETs,” IEEE Trans. Electron Devices, vol. 54, p. 115-123 (2007). CHAPTER 4 [1] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, M. Bohr, “A 90nm High Volume Manufacturing Logic Technology FeaturingNovel 45nm Gate Length Strained Silicon CMOS Transistors,” IEDM Tech. Dig., p.978-980 (2003). [2] Lim Ji-Song, S.E. Thompson, J.G. Fossum, “Comparison of Threshold-Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed n-MOSFETs,” IEEE Electron Device Lett., vol.25 p.731-733(2004). [3] Y.-C. Yeo, “Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions,” Semiconductor Science and Technology, vol. 22, S177-182 (2007). [4] ISE TCAD Tools: DESSIS, FLOOPS-ISE User's manual, ISE 10 (2004). [5] M. V. Fischetti, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” Journal of Applied Physics, vol. 80, p.2234-2252 (1996). [6] S. Thompson, G. Sun, K. Wu, J. Lim, T. Nishida, “Key Differences For Process-induced Uniaxial vs. Substrate-induced Biaxial Stressed Si and Ge Channel MOSFETs,” IEDM Tech. Dig., p. 221-224 (2004). [7] C. S. Smith, “Piezoresistance Effect in Germanium and Silicon,” Physical Review B, vol. 95, p.42-49 (1954). [8] Y. G. Wang, D.B. Scott, J. Wu, J.L. Waller, J. Hu, K. Liu, V. Ukraintsev, “Effects of Uniaxial Mechanical Stress on Drive Current of 0.13 m MOSFETs,” IEEE Ttrans. Electron Device, Vol. 50, p.529-531(2003). CHAPTER 5 [1] T. Hiramoto, N. Tamba, M. Yoshida, T. Hashimoto, T.Fujiwara,K. Watanabe, M. Odaka, M. Usami, T. Ikeda W. Ting, D. L. Kwong, and J. Lee, "A 27 GHz Double Polysilicon Bipolar Technology on Bonded SOI with Embedded 58 μm2 CMOS Memory Cells for ECL-CMOS SRAM Applications,” IEDM Tech. Dig., p. 39-42(1992). [2] F. Sato, T. Hashimoto, H. Tezuka, M. Soda, T. Suzaki, T. Tatsumi, T. Tashiro, "A 60-GHz fT Super Self-Aligned Selectively Grown SiGe-Base (SSSB) Bipolar Transistor with Trench Isolation Fabricated on SOI Substrate and its Application to 20-Gb/s Optical Transmitter IC's,” IEEE Trans. Electron Device., vol.46, p.1332-1338(1999). [3] L.E. Larson, " Device and Technology Requirements for Next Generation Communications System‘s,” IEDM Tech. Dig., p. 737-740(2000). [4] G. Freeman, D. Ahlgren, D. R. Greenberg, R. Groves, F. Huang, G. Hugo, B. Jagannathan, S. J. Jeng, J. Johnson, K. Schonengerg, K. Stein, R. Volant, and S. Subbanna, " A 0.18 mm 90 GHz fT SiGe HBT BiCMOS, ASIC-compatible, copper interconnect technology for RF and microwave applications,” IEDM Tech. Dig., p. 569-572( 1999). [5] K. Washio, E. Ohue, H. Shimamotot, K. Oda, R. Hayami,Y. Kiyota, M.Tanabet, M. Kondo, T. Hashimotott , and T. Haradat, " A 0.2-μm 180-GHz-fmax 6.7-ps-ECL SOI/HRS Self-Aligned SEG SiGe HBT/CMOS Technology for Microwave and High-speed Digital Applications,” IEDM Tech. Dig., p.741-744(2000). [6] K. Washio, " SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems,” IEEE Trans. Electron Dev., vol.50, p. 656-668(2003). [7] J. Cai, A. Ajmera, C. Ouyang, P. Oldiges, M. Steigerwalt, K. Stein, K. Jenkins, G. Shahidi, and T. Ning, "Fully-Depleted-Collector Polysilicon-Emitter SiGe-Base Vertical Bipolar Transistor on SOI,” Symp. VLSI Tech. Dig., p. 172-173(2002). [8] Q. Ouyang, J. Cai, T. Ning, P. Oldiges, and J. B. Johnson, "A Simulation Study on Thin SOI Bipolar Transistors with Fully or Partially Depleted Collector,” Proc. IEEE BCTM, p. 28-31(2002). [9] J. Cai, M.Kumar, M. Steigerwalt, H. Ho, K. Schonenberg, K.Stein, H. Chen, K. Jenkins, Q. Ouyang, P. Oldiges, and T. Ning, " Vertical SiGe-Base Bipolar Transistors on CMOS-Compatible SO1 Substrate,” Proc. IEEE BCTM, p. 215-218(2003). [10] G. Avenier, T. Schwartzmann, P. Chevalier, B. Vandelle, L. Rubaldo, D. Dutartre, L. Boissonnet, F. Saguin, R. Pantel, S. Fregonese, C. Maneux, T. Zimmer, and A. Chantre, "A self-aligned vertical HBT for thin SOI SiGeC BiCMOS,” Proc. IEEE BCTM , p.128-131(2005). [11] G. Avenier, P. Chevalier, B. Vandelle, D. Dutartre, F. Saguin, S. Fregonese, T. Zimmer, and A. Chantre, "Investigation of fully-and partially-depleted self- aligned SiGeC HBTs on thin film SOI,” Proc. ESSDERC, p.133-136(2005). [12] A. Chantre, G. Avenier, P. Chevalier, B. Vandelle, F. Saguin, C. Maneux, D. Dutartre, and T. Zimmer, "SiGe HBT design for CMOS compatible SOI,” Proc. ISTDM, p. 268-269(2006). [13] P. Chevalier, B. Barbalat, L. Rubaldo, B. Vandelle, D. Dutartre, P. Bouillon, T. Jagueneau, C. Richard, F. Saguin, A. Margain, A. Chantre, "300 GHz fmax self-aligned SiGeC HBT optimized towards CMOS compabitility,” Proc. BCTM, p. 120-123(2005). [14] DESSIS User's Manual, ISE, 2002. [15] R. Singer, D. L. Harame, and M. M. Oprysko, Silicon Germanium Technology, Modeling, and Design, New York, John Wiley. & Sons, inc. p. 89(2004). [16] N. Bovolon, P. Baureis, J.-E. Muller, P. Zwicknagl, R. Schultheis, and E. Zanoni, "A Simple Method for The Thermal Resistance Measurement of AlGaAs/GaAs Heterojunction Bipolar Transistors,” IEEE Trans. Electron Device, vol.45, p.1846-1848(1998). [17] P. Palestri, A. Pacelli, M. Mastrapasqua, "Thermal resistance in Si1-xGex HBTs on bulk-Si and SOI substrates,” Proc. BCTM, p.98-101(2001). [18] J. -S. Rieh, D. Greenberg, B. Jagannathan, G. Freeman, S. Subbanna, "Measurement and Modeling of Thermal Resistance of High Speed SiGe Heterojunction Bipolar Transistors,” Proc. Topical Meeting Silicon Monolithic Integrated Circuits in RF Systems, p. 110-113(2001). [19] T. Vanhoucke, H. M. J. Boots, and W. D. Van Noot, "Revised Method for Extraction of the Thermal Resistance Applied to Bulk and SOI SiGe HBTs,” IEEE Electron Device Lett. vol. 25, p.150-152(2004). [20] Z. Matutinovic-Krystelj, V. Venkataraman, E. J. Prinz, J. C. Sturm, C. W. Magee, " Base Resistance and Effective Bandgap Reduction in n-p-n Si/Sil-xGex/Si HBTs with Heavy Base Doping,” IEEE Trans. Electron Dev., vol.43, p. 457-466(1996). [21] J. S. Yuan, SiGe, GaAs and InP Heterojunction Bipolar Transistors, New York, John Wiley. & Sons, inc., p. 6(1999). [22] D. B. Klaassen, "A unified mobility model for device simulation—Parts I and II,” Solid-State Electron, vol. 35, p. 953-959 and p. 961-967(1992). [23] F.M. Bufler, P. Graf, B. Meinerzhagen, B. Adeline, M. M. Rieger, H. Kibbel, G. Fischer, " Low- and High-Field Electron-Transport Parameters for Unstrained and Strained Si1-x Gex,” IEEE Electron Dev. Lett., vol. 18, p.264-266(1997). [24] T. K. Cams, S. K. Chun, M. O. Tanner, K. L. Wang, T. I. Kamins, J. E. Turner, D. Y. C. Lie, M. A. Nicolet, and R. G. Wilson, " Hole Mobility Measurements in Heavily Doped Sil-xGex Strained Layers,” IEEE Trans. Electron Dev. vol.41, p. 1273-1281(1994). [25] E. J. Printz and J. C. Sturm," Current Gain-Early Voltage Products in Heterojunction Bipolar Transistors with Nonuniform Base Bandgaps,” IEEE Electron Dev. Lett., vol.12, p. 661-663(1991). [26] J. W. Slotboom and H. C. de Graaff, " Measurements of bandgap narrowing in Si bipolar transistors,” Solid-State Electron., vol.19, p.857-862 (1976). [27] HS Carslaw and JC Jaeger. Conduction of Heat in Solids, 2nd ed. Oxford University Press, 1959.zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/17106-
dc.description.abstractThis dissertation is to explore novel Si-based materials and devices. A comprehensive study of the electron mobility of strained silicon-based materials and simulation of novel silicon-based devices are presented. To study the impact of strain on the electron mobility of silicon-based materials, a theoretical model for the electron mobility in strained and relaxed Si1-xCx alloys is used. Electron mobility in strained Si1-xCx layers grown on a Si substrate and relaxed alloys were calculated as functions of carbon content, alloy scattering potential, and doping concentrations at room temperature. The use of the electron mobility model is justified through comparing with experimental data. In the case of doped strained Si1-xCx, the results of our mobility model calculation indicates that for systems with a doping concentration greater than 1018cm-3 there is no substantial decrease in the in-plane mobility with an increase in the carbon mole fraction. However, for low doping concentrations, the mobility decreases considerably as the carbon mole fraction decreases. In addition, the physical mechanisms of electron mobility and ballistic drain current enhancement by stress were investigated. The stress-induced split of the conduction band edge and effective mass change are quantitatively evaluated from modified higher order k.p band calculations. It was experimentally and theoretically demonstrated that the energy surface of the 2-fold valleys in Si NMOSFETs on a (001) wafer is particularly warped due to uniaxial [110] stress. This results in a lighter transverse effective mass of 2-fold valleys parallel to the stress. The physical reasons for the warped subband structure and abnormal mobility enhancement by uniaxial stress are investigated in this study. The variation rates of experimental electron mobility data in NMOSFETs on (001) wafer orientations under a <110> uniaxial stress as a function of the channel direction are analyzed theoretically. The limits of electron mobility enhancement and the effectiveness of stress engineering in enhancing the ballistic drain current of NMOSFETs is also discussed. In this thesis, two major novel silicon-based devices were studied. The researches investigated the stress distribution in the Si channel regions of a SiC source/drain and CESL NMOSFETs with various widths by 3D simulations. The mobility enhancement is found to be dominated by the tensile stress along the transport direction. Stress along the width direction was found to have the least effect on the drain current. The compressive stress along the vertical direction perpendicular to the gate oxide (Szz) contributes significantly to the mobility enhancement and cannot be neglected in NMOSFETs with a width between 0.05 μm and 1 μm. The impact of width on performance improvements such as the drive current gain is also analyzed. Using ISE-TCAD device simulator, the performance of SiGe HBTs with SOI substrates were investigated. In this work, the device electrical characteristics of DC, AC, and self-heating effect are studied by device simulation. Compared with the bulk SiGe HBT, simulation results show that the buried oxide layer is able to reduce the capacitance of CCS. Furthermore, the maximum oscillation frequency is improved. The study demonstrates that the SOI structure greatly improves the frequency performance of SiGe HBT and hence is applicable in high speed and high power IC. On the other hand, the buried oxide serves as an effective blockade for the locally generated heat, thus increasing the thermal resistance. The maximum oscillation frequency increases with increasing buried oxide thickness and tends to saturate accordingly. As thermal resistance of the transistor is observed to increase only slightly when the buried oxide thickness increased from 0.05μm to 0.15μm, the optimized buried oxide thickness obtained by considering these two competing factors is estimated to be approximately 0.15 μm. Finally, the researches summarize the work performed in this dissertation, and conclude the dissertation with indications of some future directions of research.en_US
dc.description.abstract本論文之目的在於仔細探究新穎之矽基材料與元件。研究內容詳實、廣泛的探究應變矽基材料的電子遷移率並且針對兩種新穎矽基元件之特性進行模擬分析。 對於探討應變效應在矽基材料的電子遷移率所造成之影響,本研究採用一個適用於矽碳合金在應變與鬆弛狀況下之電子遷移率的理論計算模型。透過理論的計算,分別做出在室溫之情況下,應變矽碳成長於矽基板、矽碳合金上電子遷移率與碳含量、合金散射位勢、摻雜濃度的關係。為使理論計算模型彰顯公信,本研究利用實驗結果對理論計算模型加以檢視、確認。根據本研究的計算結果顯示,摻雜濃度高於1018cm-3時,碳的莫耳分數增加不會造成水平方向遷移率的顯著下降;而在較低摻雜時,水平方向、鉛直方向遷移率則均會隨著碳的莫耳分數減少而下降。 除此之外,本研究也仔細探討單軸應力影響矽基材料載子遷移率的物理原因。單軸應力會造成次能帶結構變形並導致異常的遷移率提昇。本研究使用了考慮二階微擾項次之k‧p能帶計算方法,採用伴隨著應力之加入所造成之次能帶的結構參數,例如能帶邊緣之分裂、有效質量之改變,對電子之遷移率進行定量分析與計算。本研究發現在[110]方向之單軸應力會導致平行於應力方向之z-能谷的有效質量變小,並使矽基場效電晶體z-能谷之能量面變形。利用引入應力的次能帶結構參數計算方式,本研究精確的建立了矽基材料在[110]方向(亦即,φ = 0)之單軸應力作用下,電子遷移率與通道方向(亦即,θ)的關係。對於電子遷移率提升的極限、應力工程於提升N型MOSFETs 彈道汲極電流的機制亦一倂加以探討。 在此論文中,本研究探討兩個重要的應變矽基元件,分別為含有矽碳合金與接觸孔蝕刻停止層製程之N型金氧半場效電晶體以及絕緣層上覆矽之矽鍺雙極性接面電晶體。在金氧半場效電晶體(MOSFET)的通道中形成應變的方式甚多,通常可藉由部分製程步驟、材料上自然晶格常數的差異或是元件封裝等等方式來達成。接觸孔蝕刻停止層(contact etch stop layer,CESL) 是製程系統形成應變的製程步驟之一,通道內的應變可由此部分製程步驟所產生。在此,本研究針對通道材料為矽、源極和汲極材料為碳化矽的N型金氧半場效電晶體進行各種寬度的矽通道區應力分布的三維模擬分析研究。研究結果顯示,在傳輸方向伸張應力支配了主要的載子遷移率的提昇作用;沿著寬度方向之應力對汲極電流影響則最微弱;沿著鉛直方向的壓縮應力垂直於閘極氧化層,對載子遷移率的提昇作用最鉅。根據研究顯示,N型金氧半場效電晶體的寬度介於0.05 μm至1 μm時,鉛直方向的壓縮應力對載子遷移率的提昇具有不可忽視的影響。此外,本研究亦分析了元件寬度對其輸出性能的貢獻如驅動電流增益。 利用ISE-TCAD 元件模擬器,本研究分析絕緣層上覆矽之矽鍺雙極性接面電晶體的元件特性。主要的模擬演算是針對元件的直流、交流等電學特性,以及元件的自我加熱效應。模擬結果顯示,在與傳統的塊材結構相互比較之下,絕緣層上覆矽的結構因埋氧化層的加入,具有降低集基極之間的電容CCS。此外,本研究亦發現埋氧化層的加入亦提昇了元件的最大振盪頻率,因而極適用於高速與高功率IC。反之,埋氧化層在元件中卻也扮演著阻擋熱傳導的工作,所以會提昇元件熱阻。本研究發現最大振盪頻率隨著埋氧化層增厚而增加,最後趨於飽和。由於當埋氧化層厚度介於0.05 μm至0.15 μm時,電晶體的熱阻僅有些微增加,本研究得到元件埋氧化層的最佳化厚度為0.15 μm。 最後,針對本論文的工作做研究的摘要整理,並提出一些未來可進行的延伸性研究構想。zh_TW
dc.description.tableofcontentsCONTENTS CHAPTER 1 I NTRODUCTION…………………………………………………1 1.1 Motivation for Dissertation………………………………………………….3 1.2 Organization of Dissertation………………………………………………...5 CHAPTER 2 THEORETICAL STUDY OF ELECTRON MOBILITY FOR SILICON- CARBON ALLOYS…………………………………………………7 2.1 Introduction………………………………………………………………….7 2.2 Theory……………………………………………………………………….8 2.2.1 Energy Band Structure……………………………………………...8 2.2.2 Scattering Mechanisms…………………………………………….11 2.2.3 Mobility Calculations……………………………………………...16 2.3 Results and Discussions…………………………………………………..17 2.4 Summary………………………………………………………………….25 CHAPTER 3 IMPACT OF STRESS ENGINEERING ON ELECTRON MOBILITY AND BALLISTIC CURRENT FOR STRAINED SI NMOSFETS……………………………………………………………………..26 3.1 Introduction………………………………………………………………...26 3.2 Deformation Effects on Si Conduction Band……………………………...27 3.3 Subband Structure in the Inversion Layer…………………………………33 3.4 The Impact of Uniaxial Stress on Mobility………………………………...38 3.5 The Impact of Uniaxial Stress on Ballistic Current………………………..42 3.6 Conclusions………………………………………………………………...46 CHAPTER 4 EXPLORING THE EFFECT OF WIDTH ON THE PERFORMANCE ENHANCEMENT IN NMOSFETS WITH SILICON- CARBON ALLOY STRESSOR AND TENSILE CESL ……………………47 4.1 Introduction………………………………………………………………...47 4.2 Simulation Method and Mobility Model…………………………………..47 4.3 Results and Discussion…………………………………………………….55 4.4 Summary…………………………………………………………………...67 CHAPTER 5 THE EFFECT OF OXIDE THICKNESS ON THE PERFORMANCE OF SIGE HBTS ON THIN-FILM SOI…………………..68 5.1 Introduction……………………………………………………………….68 5.2 Device Structure Concepts and Simulation Method……………………...69 5.3 Results and Discussion…………………………………………………...73 5.3.1 The DC Performance of SOI SiGe HBTs………………………….73 5.3.2 Self-Heating and Thermal Effect…………………………………..76 5.3.3 The AC Characteristics of the SOI SiGe HBTs……………………80 5.4 Conclusion………………………………………………………………..83 CHAPTER 6 CONCLUSION AND FUTURE WORK………………………..84 6.1 Conclusion………………………………………………………………84 6.2 Future Work……………………………………………………………..87zh_TW
dc.language.isoen_USzh_TW
dc.publisher物理學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2404200800314200en_US
dc.subjectSi1-xCx alloysen_US
dc.subject矽碳合金zh_TW
dc.subjectstrainen_US
dc.subjectelectron mobilityen_US
dc.subjectSiGe HBTen_US
dc.subjectSOIen_US
dc.subject應變zh_TW
dc.subject電子遷移率zh_TW
dc.subject矽鍺異質接面電晶體zh_TW
dc.subject絕緣層上覆矽zh_TW
dc.titleStudy of the electron mobility and simulation of novel devices of strained silicon-based materialsen_US
dc.title應變矽基材料電子遷移率之計算與應變矽基新穎元件模擬研究zh_TW
dc.typeThesis and Dissertationzh_TW
Appears in Collections:物理學系所
文件中的檔案:

取得全文請前往華藝線上圖書館



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.