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A Study of the Current-Mode Sense Amplifier for Low-Power and High-Speed SRAM
|摘要:||Because of the improvement of VLSI process technology, many electronic components can be condensed into a single chip. Thus, the requirement of area, speed and power consumption is becoming more and more critical. How to design a circuit with a low power and high speed is one important issue in the future. In this thesis, a low power consumption and high speed current sense amplifier has been proposed to achieve the read/write operation for a SRAM. A very few voltage difference existing between the bit pair will induce the effective sense activity in our proposed sense amplifier. In addition, an isolated mechanism has been applied in our research to reduce the power consumption effectively. Meanwhile, there are several experiments have been implemented while considering different bit line loading, output loading and supply voltage. The experimental results show that a better performance has been obtained as comparing with other methods. Finally, we also implement our proposed sense amplifier with a 2K bits SRAM, and prove it can work correctly.|
|Appears in Collections:||資訊科學與工程學系所|
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