Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/18998
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dc.contributor.advisor黃德成zh_TW
dc.contributor.author黃勇仁zh_TW
dc.contributor.authorHuang, Yung-Jenen_US
dc.contributor.other中興大學zh_TW
dc.date2008zh_TW
dc.date.accessioned2014-06-06T07:05:59Z-
dc.date.available2014-06-06T07:05:59Z-
dc.identifier.urihttp://hdl.handle.net/11455/18998-
dc.description.abstractBecause of the improvement of VLSI process technology, many electronic components can be condensed into a single chip. Thus, the requirement of area, speed and power consumption is becoming more and more critical. How to design a circuit with a low power and high speed is one important issue in the future. In this thesis, a low power consumption and high speed current sense amplifier has been proposed to achieve the read/write operation for a SRAM. A very few voltage difference existing between the bit pair will induce the effective sense activity in our proposed sense amplifier. In addition, an isolated mechanism has been applied in our research to reduce the power consumption effectively. Meanwhile, there are several experiments have been implemented while considering different bit line loading, output loading and supply voltage. The experimental results show that a better performance has been obtained as comparing with other methods. Finally, we also implement our proposed sense amplifier with a 2K bits SRAM, and prove it can work correctly.en_US
dc.description.tableofcontents誌謝 i 中文摘要 ii 英文摘要 iii 目錄 iv 表目錄 vi 圖目錄 vii 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 3 1.3 研究方向 4 1.4 章節概要 4 第二章 背景知識與相關研究 6 2.1 感測放大器簡介 6 2.1.1 感測放大器之功能與要求 6 2.1.2 感測放大器之分類 7 2.2 傳統電壓式感測放大器 10 2.2.1 傳統差動感測放大器 10 2.2.2 傳統正回授感測放大器 13 2.2.3 改良式正回授感測放大器 15 2.3 電流式感測放大器 16 2.3.1 Clamped Bit-Line Sense Amplifier 16 2.3.2 Simple Four Transistor Sense Amplifier 18 2.3.3 Hybrid Sense Amplifier 21 2.3.4 New Hybrid Current Sense Amplifier 22 2.3.5 S.M. Wang’s Sense Amplifier 24 第三章 研究內容 26 3.1感測放大器 26 3.2 感測放大器的模擬與比較 35 3.2.1 感測放大器之模擬環境 35 3.2.2 一般條件下的模擬與比較 37 3.2.3 輸入負載(位元線負載)變化下的模擬與比較 40 3.2.4 輸出負載變化下的模擬與比較 44 3.2.5 工作電壓變化下的模擬與比較 48 3.2.6 感測放大器之電晶體大小模擬 51 3.2.7 感測放大器所負載之記憶單元數之模擬 53 3.3 蒙地卡羅分析模擬 55 3.4 總結 63 第四章 晶片設計 64 4.1 記憶體架構與操作 64 4.1.1 記憶體架構說明 64 4.1.2 記憶體操作方式 67 4.2 記憶體電路說明 68 4.2.1 控制訊號電路 68 4.2.2 列/行解碼器 69 4.2.3 輸入暫存器 72 4.2.4 寫入電路 73 4.2.5 記憶單元 74 4.3 模擬結果 77 4.3.1 周邊控制訊號電路模擬 78 4.3.2 寫入動作模擬 79 4.3.3 讀出動作模擬 81 第五章 結論與未來工作 83 參考文獻 84zh_TW
dc.language.isoen_USzh_TW
dc.publisher資訊科學與工程學系zh_TW
dc.subjectSense Amplifieren_US
dc.subject感測放大器zh_TW
dc.subjectSRAMen_US
dc.subjectLow-poweren_US
dc.subject靜態隨機存取記憶體zh_TW
dc.subject低功耗zh_TW
dc.title低功率與高速靜態隨機存取記憶體電流模式感測放大器之研究zh_TW
dc.titleA Study of the Current-Mode Sense Amplifier for Low-Power and High-Speed SRAMen_US
dc.typeThesis and Dissertationzh_TW
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