Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/1921
標題: 利用單一變壓耦式蝕刻以形成具有一對矽尖角之微渠道製程之研究
A Study of a Single Transformer Coupled Plasma Etching Process for Forming a Micro-Channel with a Pair of Silicon Tips
作者: 陳志銘
Chen, Chih-Ming
關鍵字: TCP plasma etching
變壓耦式電漿蝕刻
floating gate
silicon tip
bottom dimple
快閃記憶體
浮置閘極
矽尖角
矽凹縫
出版社: 機械工程學系
摘要: 此論文主要研究一種單一變壓耦式(TCP)蝕刻方法以形成具一對矽尖角之微渠道製程,此具矽尖角之微渠道可當做快閃記憶體中之浮置閘極,以提高其資料抹除之效率。研究過程中首先製作含有一矽層之基底,然後將該基底置於一蝕刻機台之反應室中,利用蝕刻氣體並施以一射頻功率回蝕上述之矽層,以使被蝕刻矽層之中間低於兩側,以構成一對矽尖角。研究中分別討論蝕刻氣體之成分、反應室壓力與射頻功率對矽尖角之角度與基底矽層底部凹缝形成之影響,所考慮之蝕刻氣體由不等比例之氯氣(Cl2)、氧氣(O2)、氦氣(He)、溴化氫(HBr)所組成;蝕刻機台之上射頻功率固定為600 W,下射頻功率分別考慮為10 W與20 W;而反應室壓力則分別為4、5、6 與10 mTorr;研究之結果發現,在下射頻功率為20 W,而反應室壓力設定為10 mTorr的條件下,當調整蝕刻氣體中之氯氣為20.4%、氧氣為5.5%、氦氣為12.9%與溴化氫為61.2%時,以進行乾式蝕刻,即可形成一底部無凹縫之矽尖角。
A single transformer coupled plasma dry etching (TCP) process for forming a micro-channel with a pair of silicon tips was investigated. This micro-channel can act as a floating gate in a flash memory to increase erase speed. In each experiment, a substrate with a silicon layer was carefully prepared. This substrate was placed in the reaction chamber of a TCP etching machine. By passing an etching gas mixture through the substrate and processing it with a radio frequency power, a concavity was formed on the silicon layer. The middle region at the bottom of the concavity would be lower than the edge region, a silicon tip was thus obtained. In this work, the effects of etching gas composition, chamber pressure and radio frequency power on the angle of silicon tip and bottom dimple were investigated. The considered etching gas mixture comprises of Cl2, O2, HBr, and He. The upper radio frequency power was fixed at 600 W and the lower radio frequency power was either at 10 W or at 20 W. Three chamber pressures, 4.5, 6, and 10 mTorr, were individually considered. The result shows that for the case with the lower radio frequency power of 20 W, chamber pressure of 10 mTorr and the Cl2, O2, HBr, and He composition setting at 20.4%, 5.5%, 12.9%, 61.2%, a silicon tip without bottom dimple can be formed.
URI: http://hdl.handle.net/11455/1921
Appears in Collections:機械工程學系所

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