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標題: 常用運算碼編碼的低功率指令快取記憶體
Frequent Opcode Encoding for Low Power Instruction Cache
作者: 賴柏宇
Lai, Po-Yu
關鍵字: Low Power Instruction Cache
Hot Instruction
出版社: 資訊科學系所
引用: [1] B. D. Yang and L. S. Kim, “A Low-Power SRAM Using Hierarchical Bit Line and Local Sense Amplifiers, ” IEEE J. Solid-State Circuits 2005, vol. 40, pp. 1366 - 1376 [2] R. E. Aly, M. A. Bayoumi, and M. Elgamel, “Dual Sense Amplified Bit Lines (DSABL) Architecture for Low-Power SRAM Design,”IEEE Conf. International Symposium on Circuits and Systems 2005, vol. 2, pp.1650 - 1653 [3] C. Thondapu, P. Elakkumanan, and R. Sridhar, “RG-SRAM: A Low Gate Leakage Memory Design, ” IEEE Conf. Computer Society Annual Symposium on VLSI 2005, pp. 295 - 296 [4] L. Villa, M. Zhang, and K. Asanovic, “Dynamic Zero Compression for Cache Energy Reduction,” IEEE Conf. 33rd Annual IEEE/ACM International Symposium on Microarchitecture 2000, pp. 214 - 220 [5] K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy Caches: Simple Techniques for Reducing Leakage Power,” IEEE Conf. 29th Annual International Symposium on Computer Architecture 2002, pp. 148 - 157 [6] N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, “Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power, ” IEEE Tran. Very Large Scale Integration (VLSI) Systems 2004, vol. 12, pp.167 - 184 [7] K. J. Kim, C. H. Kim, and K. Roy, “TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique,” IEEE Conf. Sixth International Symposium on Quality of Electronic Design 2005, pp. 59 - 64 [8] J. L. Hennessy, and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd edition , Morgan Kaufmann Publishers, San Francisco CA, 2003. [9] [Online].Available: [10] J.L. Ayala, M.L Vallejo, A. Veidenbaum, and C.A. Lopez, “Energy Aware Register File Implementation through Instruction Predecode,” in Proc. IEEE International Conference on Application-Specific Systems, Architectures, and Processors 2003 [11] J. H. Tseng and K. Asanovic, “Energy-Efficient Register Access,” in Proc. 13th Symp. Integrated Circuits and Systems Design, IEEE Press, 2000, pp. 377-382. [12] K. Nii, Y. Tsukamoto, T. Yoshizawa, S. Imaoka, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino, and S. Iwade, “A 90-nm Low-Power 32-kB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile Applications, ” IEEE J. Solid-State Circuits 2004, vol. 39, Issue 4, pp. 684 - 693 [13] K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits”. In Proceedings of the IEEE 2003, vol. 91, Issue 2, pp. 305-327 [14] T. Austin, E. Larson, and D. Ernst, “SimpleScalar: an infrastructure for computer system modeling, ” Computer, vol. 35, Issue 2, pp. 59 - 67, Feb. 2002 [15] The Standard Performance Evaluation Corporation (SPEC), “SPEC CPU2000 V1.3 Documentation, ” URL:
摘要: 在本論文中,我們將提出一個低功率的指令快取記憶體(Low Power Instruction Cache)。利用指令快取記憶體的「熱指令」現象,也就是有某些指令會經常出現的現象,我們挑選3道佔了整個程式平均約60%的熱指令重新編碼來儲存,並切斷原本快取記憶體相對應的欄位之供應電源,以降低靜態與動態之功率消耗。本電路使用台積電 0.18 μm 1P6M 製程來設計並完成驗證,整個快取記憶體大小為32 行 × 128 列。經由實驗模擬,快取記憶體內約有40%~65%存放的是熱指令;另外,對於我們所提出的快取記憶體 ,其在讀取熱指令時約可節省14%的動態功率消耗;其在熱指令佔55%時約可節省11%靜態功率消耗。
In this paper we introduce a low-power instruction cache memories (I-Cache), which exploits the prevalence of “hot instruction” stored in the I-Cache. In order to reduce static and dynamic power, we also take advantage of the hot instruction to cut off supply voltage of opcode field. Simulation results show that we can reduce dynamic power by around 14% while reading hot instruction and reduce static power by around 11% when hot instruction accounts for 55%.
其他識別: U0005-2108200616230700
Appears in Collections:資訊科學與工程學系所



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