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標題: 使用分段以及條件放電減低內容可定址記憶體功耗
Using Segmentation and Conditional Discharge to Reduce Power Consumption of CAM
作者: 廖元宏
Liao, Yuan-Hong
關鍵字: CAM
Conditional Discharge
出版社: 資訊科學系所
引用: [1] T. Ogura, M. Nakanishi, T. Baba, Y. Nakabayashi, and R. Kasai, “A 336-kbit Content-Addressable Memory for Highly Parallel Image Processing,” in Proc. IEEE Custom Integrated Circuits Conf. 1996, pp. 273-276. [2] M. Motomura, J. Toyoura, K. Hirata, H. Ooka, H. Yamada, and T. Enomoto, “A 1.2-Million Transistor 33-MHz 20-b Dictionary Search Processor (DISP) ULSI with a 160-kb CAM,” IEEE J. Solid-State Circuits 1990, vol. 25, pp. 1158-1165. [3] T. Takayanagi, K. Sawada, M. Takahashi, Y. Itoh, M. Uchida, Y. Toyoshima, H. Hayashida, and M. Norishima, “2.6 Gbytes/s Bandwidth Cache/TLB Macro for High-Performance RISC Processor,” in Proc. IEEE Custom Integrated Circuits Conf. 1991, pp. 10.2.1-10.2.4. [4] K. J. Lin, C. W. Wu, and S. Member, “A Low-Power CAM Design for LZ Data Compression,” IEEE Tran. Computers 2000, vol. 49, no. 10, pp. 1139-1145. [5] R. Djwmal, G. Mazare, and G. Michel, “Toward Reconfigurable Associative Architecture for High Speed Communication Operators,” in Proc. IEEE Engineering of Computer Based Systems 1996, pp. 74-79. [6] C. S. Lin, K. H. Chen, and B. D. Liu, “ Low-Power and Low-Voltage Fully Parallel Content-Addressable Memory,” in Proc. IEEE International Symposium on Circuits and Systems 2003, vol.5, pp. 373-376. [7] K. Pagiamtzis and A. Sheikholeslarni, “Pipelined Match-Lines and Hierarchical Search-lines for Low-Power Content-Adressable Memories,” in Proc. IEEE Custom Integrated Circuits Conf. 2003, pp.21-24. [8] I. Arsovski, T. Chandler and A. Sheikholeslami, “A Ternary Content-Addressable Memory (TCAM) Based on 4T Static Storage and Including a Current-Race Sensing Scheme,” IEEE J. Solid-State Circuits 2003, pp. 155 - 158. [9] K. H. Cheng, C. H. Wei and S. Y. Jiang, “Static Divided Word Matching Line for Low-Power Content Addressable Memory Design,” in Proc. IEEE International Symposium on Circuits and Systems 2003, vol.2, pp. 23-26. [10] I. Y.-L. Hsiao, D. H. Wang and C. W. Jen, “Power Modeling and Low-Power Design of Content Addressable Memories,” in Proc. IEEE International Symposium on Circuits and Systems 2001, vol.4, pp. 926 - 929. [11] C. S. Lin, J. C. Chang, B. D. Liu, “A Low-Power Precomputation-Based Fully Parallel Content-Addressable Memory,” IEEE J. Solid-State Circuits 2003, pp. 654 - 662. [12]A. Efthymiou and J. D. Garside, “A CAM With Mixed Serial-Parallel Comparison for Use in Low Energy Caches,” IEEE Tran. Very Large Scale Integration Systems 2006, Vol.12, pp. 325-329. [13]B. D. Yang, L. S. Kim, “A Low-Power CAM Using Pulsed NAND-NOR Match-Line and Charge-Recycling Search-Line Driver, ” IEEE J. Solid-State 2005 , pp. 1736 - 1744 .
摘要: 本論文中,我們將提出一個使用在低功率快取記憶體的內容可定址記憶體(Content Addressable Memories, CAM)架構,結合分段及條件式放電的技術,以達到低功率以及高效能的目的。相較於傳統CAM的設計,我們所提出的架構由於使用條件式放電,所以能夠大幅度的降低搜尋時所需的功率。而效能方面由於使用分段技術,搜尋速度可達到與傳統NOR-TYPE CAM相同的速度。本設計使用TSMC 0.18μm 1P6M製程來設計並驗證電路,電路大小為32*128。實際模擬結果在1.8v的供應電壓下,能夠節省大約88%的相符線功率,並且對效能不會造成任何的影響。
In this paper we proposed a low-power and high-performance CAM used in cache system. In our design, we use the conditional discharge technique to reduce the power consumption of CAM, and use the segmentation method to retain the same performance as the traditional NOR-type CAM design. The whole design was fabricated with the TSMC 0.18um 1P6M CMOS process. With 128x32 CAM size, measurement results indicate that our design can reduce 88% power dissipation compare to tradition CAM design at 1.8v supply voltage.
其他識別: U0005-2108200616460100
Appears in Collections:資訊科學與工程學系所



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