Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/19378
標題: 佈局考量之掃描鏈重新排序以提高歪斜載入轉態測試涵蓋率
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage
作者: 彭國霖
Peng, Kuo-Lin
關鍵字: scan chain
掃描鏈
transition fault
skewed-load
layour
wire length
轉態錯誤
歪斜載入
佈局
繞線長度
出版社: 資訊科學系所
引用: [1] Z. Barzilai and B. Rosen, “Comparison of AC self-testing procedures,” in Proc. Int'l Test Conf., pp. 89-94,1983. [2] E. P. Hsieh et al., “Delay test generation,” in Proc. Design Automation Conf., pp. 486-491, 1977. [3] Y. K. Malaiya and R. Narayanswamy, “Testing for timing faults in synchronous sequential integrated circuits,” in Proc. Int'l Test Conf., pp. 560-571, 1983. [4] T. Hayashi, “A delay test generator for logic LSI,” in Proc. Int'l Fault-Tolerant Computing Symp., pp. 146-149, 1984. [5] G.L. Smith, “Model for delay faults based upon paths,” in Proc. Int'l Test Conf., pp. 342-349, 1985. [6] J. Savir and W.H. McAnney, “Random pattern testability of delay faults,” in Proc. Int'l Test Conf., pp. 263-273, 1986. [7] C. J. Lin and S. M. Reddy, “On delay fault testing in logic circuits,” IEEE Trans. Computer-Aided Design, Vol. 6, No. 5, pp. 694-703, Sep., 1987. [8] S. M. Reddy et al., “An automatic test pattern generator for the detection of path delay faults,” in Proc. Int'l Conf. Computer-Aided Design, pp. 284-287,1987. [9] B. Dervisoglu and G. Stong, “Design for testability: using scanpath techniques for path-delay test and measurement”, in Proc. Int'l Test Conf., pp.365-374, 1991. [10] C.T. Glover and M.R. Mercer, “A method of delay fault test generation,” in Proc. Design Automation Conf., pp.90-95, 1998. [11] Y.K. Malaiya and R. Narayanaswamy, “Testing for timing faults in synchronous sequential circuits,” in Proc. Int'l Test Conf., pp.560-571, 1983. [12] J. Savir and S. Patil, “Scan-Based Transition Test,” IEEE Trans. Computer-Aided Design, pp. 1232-1241, Aug. 1993. [13] J. Savir, “ Skewed-Load Transition Test: Part I Calculus,” in Proc. Int'l Test Conf., pp. 705-713,1992. [14] S. Patil and J. Savir, “Skewed-Load Transition Test: Part II, Coverage.” in Proc. Int'l Test Conf., pp. 714-722, 1992. [15] J. Savir and S. Patil, “On Broad-Side Delay Test,” IEEE Transactions on VLSI system, Vol. 2, No. 3, pp. 368-372 Sep. 1994. [16] K.D. Boese, A.B. Kahng, and R-S. Tsay, “Scan chain optimization: heuristic and optimal solutions,” Research Report UCLA, 1994. [17] M. Feuer and C.C. Koo, “Method for rechaining shift register latches which contain more than one physical book,” IBM Tech. Disclosure Bulletin, Vol. 25, No. 9, pp. 4818-4820,1983. [18] K.H. Lin, C.S. Chen, and T.T. Hwang, “Layout driven chaining of scan flip-flops,” IEE Proc. Computers Digital Techn. Vol. 143, No. 6, pp. 421-425,1996. [19] C.S. Chen and T.T. Hwang, “Layout driven selection and chaining of partial scan flip-flops,” J. Electron. Test, Vol. 13, pp. 19-27, Apr., 1998. [20] W. Mao and M. D. Ciletti, “Arrangement of latches in scan-path design to improve delay fault coverage,” in Proc. Int'l Test Conf., pp.387-393, 1990. [21] K.T. Cheng, S. Devadas, and K. Keutzer, “Delay-fault test generation and synthesis for testability under a standard scan design methodology,” IEEE Trans. Computer-Aided Design, Vol. 12, No. 8, pp. 1217-1231, 1993. [22] R.B. Norwood and E.J. McCluskey, “Delay testing for sequential circuit with scan,” Center for Reliable Computing, Stanford University, Stanford , CA, Tech. Rep. CRC TR 97-5,1976. [23] I. Pomeranz, and S.M. Reddy, “On the coverage of delay faults in scan designs with multiple scan chains,” in Proc. Int'l Conf. Computer Design, pp. 206-209, 2002. [24] W. Li, S. Wang, S.T. Chakradhar, and S.M. Reddy, “Distance restricted Scan Chain Reordering to enhance delay fault coverage,” in Proc. Int'l Conf. VLSI Design, pp. 471-478, 2005. [25] P. Gupta, A. B. Kahng, and S. Mantik, “Routing-aware scan chain ordering,” in Proc. Asia and South Pacific Design Automation Conf., pp. 857-862, 2003. [26] P. Gupta, A.B. Kahng, I.I. Mandoiu, and P. Sharma, “Layout-aware scan chain synthesis for improved path delay fault coverage,” IEEE Trans. Computer-Aided Design, Vol. 24, No. 7, pp. 1104-1114, 2005.
摘要: 隨著製程的進步,傳統的stuck-at-fault已不敷使用,因此延遲錯誤越來越被重視。我們提出的方法可以在具有掃描架構的電路中,有效率的測試延遲錯誤。我們使用了一個佈局考量之掃描鏈重新排序的技術,不但能讓歪斜載入具有加強化掃描的高錯誤涵蓋 率,還能減少掃描鏈的繞線長度。本論文也分析了掃描細胞之間的繞線距離和錯誤涵蓋率的關係,實驗顯示了繞線距離和錯誤涵蓋率是呈現“負相關”。在本論文的最後,我們使用了ISCAS’89的電路對我們的演算法進行實驗,我們不但列出了實驗數據,也對我們的實驗數據做更詳細的分析,以顯示我們演算法能有效地讓掃描鏈具有短的繞線長度。
In this paper, we propose a layout-based scan chain ordering method to improve fault coverage for skewed-load delay test with minimum routing overhead. This approach provides many advantages over previous methods. (1) The proposed method can provide 100% test fault coverage for all detectable transition faults. (2) With layout information taken into account, the routing penalty is small, and thus the impact on circuit performance will not be significant.
URI: http://hdl.handle.net/11455/19378
其他識別: U0005-2407200609180800
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2407200609180800
Appears in Collections:資訊科學與工程學系所

文件中的檔案:

取得全文請前往華藝線上圖書館

Show full item record
 
TAIR Related Article
 
Citations:


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.