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A New Test Approach for NoC Functional Testing
|引用:|| B. Vermeulen, J. Dielissen, K. Goossens, C. Ciordas, “Bringing communications networks on a chip: test and verification implications”, IEEE Communications Magazine, Volume 41, Issue 9, sept. 2003, pp. 74-81.  E. Cota et al., “Power aware NoC Reuse on the Testing of Core-Based Systems”, Proceedings of ITC 2003, pp. 612-621.  C. Liu, E. Cota, H. Sharif and D.K. Pradhan, "Test Scheduling for network-on-chip with BIST and precedence constraints", Proceedings of ITC 2004, pp. 1369-1378.  C. Liu, V. Iyengar, J. Shi, E. Cota, "Power-aware Test Scheduling in network-on-chip using varible-rate on-chip clocking", Proceedings of VTS 2005, pp. 349-354.  C. Grecu, P. Pande, B. Wang, A. Ivanov and R. Saleh,“Methodologies and algorithms for testing switch-based NoC interconnects,” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,pp. 238-246, 2005.  P. Pande, C. Grecu, A. Ivanov, R. Saleh, and G. De Micheli, “Design, Synthesis, and Test of Networks on Chips,” IEEE Des. Test Comput., vol. 22, no. 5, pp. 404-413, Sep./Oct. 2005.  Laung-Terng Wang, Charles E. Stroud, Nur A. Touba, System-on-Chip Test Architectures, Morgan Kaufmann Publishers, San Francisco, CA, USA, 2007.  K. Stewart, S. Tragoudas, "Interconnect Testing for Networks on Chips", Proceedings of VTS 2006, pp. 100-105.  A. M. Amory, E. Briao, E. Cota, M. Lubaszewski, and F. G. Moraes, “A scalable test strategy for network-on-chip routers,” in Proc. IEEE ITC, 2005, pp. 591-599.  M. Hosseinabadi, A. Dalirsani, and Z. Navabi, “Using the Inter- and Intra-Switch Regularity in NoC Switch Testing,” Proc. Design Automation and Test in Europe(DATE), 2007, pp. 361-366.  M. Cuviello, S. Dey, X. Bai, and Y. Zhao, “Fault Modeling and Simulation for Crosstalk in System-on- Chip Interconnects,” Proc. IEEE/ACM International Conference on Computer-Aided Design, 1999, pp. 297-303.  C. Grecu, P. Pande, A. Ivanov, and R. Saleh, “BIST for Network-on-Chip interconnect infrastructures,” Proc. 24th IEEE VLSI Test Symposium (VTS'06), 2006, pp. 30-35.  A. Alaghi, N. Karimi, M. Sedghi, and Z. Navabi, “Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model”, Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Rome, Italy, September 2007, pp. 21-29.  M. Sedghi, A. Alaghi, E. Koopahi, and Z. Navabi, “An HDL-Based Platform for High Level NoC Switch Testing”, Proc. Asian Test Symposium (ATS), Beijing, China, October 2007, pp. 453-458.  M. Sedghi, E. Koopahi, A. Alaghi, M. Fathy, and Z. Navabi, “An Exhaustive Test Strategy Based on Flooding routing for NoC Switch Testing”, Proc. IEEE East-West Design and Test Symposium (EWDTS), Yerevan, Armenia, September 2007, pp. 262-267.  M. Sedghi, E. Koopahi, A. Alaghi, M. Fathy, Z. Navabi, "An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations" ,VLSI Design 2008: 409-414  D. Wiklund, and D. Liu, Design of a System-on-Chip Switched Network and its Design Support, in the Proceedings of the International Conference on Communications, Circuits and Systems (ICCCAS), Vol. 2, pages 1279-1283, June 2002.  Z. Lu and A. Jantsch, Flit Admission in On-Chip Wormhole- Switched Networks with Virtual Channels, Proceedings of International Symposium on System-On-Chip, November 2004.  A. Radulescu, J. Dielissen, S. G. Pestana, O. P. Gangwal, E. Rijpkema, P.Wielage, and K. Goossens, An Efficient On-Chip NI Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration, IEEE Transactions on Computer-Aided Design, Vol. 25, NO. 1, pages 4-17, January 2005.  K. Goossens, J. Dielissen, and A. Radulescu, AEthereal Network on Chip: Concepts, Architectures, and Implementations, IEEE Design and Test of Computers, Vol. 22, No. 5, pages 414-421, October 2005.  C. A. Zeferino, M. E. Kreutz, L. Carro and A. A. Susin. A Study on Communication Issues for System-on-Chip. Proceedings of the 15th Symposium on Integrated Circuits and System Design (SBCCI), 2002.  Tobias Bjerregaard ,Shankar Mahadevan ,”A survey of research and practices of Network-on-chip,” ACM Computing Surveys (CSUR) ,Volume 38 , Issue 1, Article No.1, Year of Publication: 2006  C. Grecu, A. Ivanov, Resve A. Saleh, P. Pratim Pande: Testing Network-on-Chip Communication Fabrics. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2201-2214 (2007)  Atefe Dalirsani, Mohammad Hosseinabadi, Zainalabedin Navabi, “An Analytical Model for Reliability Evaluation of NoC Architectures”, Proceedings of International On-Line Testing Symposium 2007.  L. Benini, G. de Micheli, “Networks on chips: a new SoC paradigm” Computer, Volume: 35, Issue: 1, Jan. 2002, pp: 70 - 78.  L. M. Ni and P. K. McKinley, “A Survey of Wormhole Routing Techniques in Direct Networks,” IEEE Transactions on Computers, vol. 26, pp.62-76, February 1993.  W. J. Dally and C. L. Seitz, “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,” IEEE Trans. On Computers, vol. 4, no. 12, November 1993.  P. Guerrier and A. Greiner,”A Generic Architecture for On-Chip Packet-Switched Interconnections,” Proceedings of the conference on Design, automation and test in Europe, p.250-256, March 27-30, 2000.  W. J. Dally and B. Towels, “Route, Packets, Not Wires: On-Chip Interconnection Networks, ” Proceedings of IEEE Design Automation Conference, pp. 684--689. , 2001.  W. Cesario, A. Baghdadi, L. Gauthier, and D. Lyonnard, “Component-Based Design Approach for Multicore SoCs,” Proc. 39th Design Automation Conf. (DAC02), ACM Press, New York 2002, pp. 789-794.  I. Saastamoinen, D. Siguenza-Tortosa, and J. Nurmi, “Interconnect IP node for future system-on-chip designs”, The First IEEE International Workshop on Electronic Design, Test and Applications. (DELTA ''02), Christchurch, New Zealand, January 2002.  S. Yoo, G. Nicolescu, D. Lyonnard, A. Baghdadi, and A. A. Jerraya, “A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design,” Int. Symposium on HW/SW Codesign (CODES), Copenhagen, Denmark, April 2001, pp. 195-200.|
Network-on-chip (NoC) communication fabrics will be increasingly used in many large multi-core system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test cost. Structural tests have deficiencies in terms of hardware overhead and test application time which is bypassed by functional tests. In this paper, we analyzed the functional fault models and present a new test approach for testing such NoC architectures. The fault models used are specific to router switch, network interface, and channels between them. The novelty of our approach lies in the using the regularity of the 2D-Mseh NoC structures to concurrently transport test packet without congestions. This mechanism reduced the test time and, implicitly, the test cost. Experimental results show the efficiency that it is able to reduce the test time significantly and 100% router switch port fault coverage, as compared with the other literatures.
|Appears in Collections:||資訊科學與工程學系所|
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