Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/19786
標題: 一種抑制串音雜訊的方法
A Crosstalk-Induced Noise Reduction Method
作者: 劉志偉
Liu, Chi-Wei
關鍵字: 耦合效應
雜訊訊號的完整性(SI)
錯誤模型
能量
功率消耗
漏電流
出版社: 資訊科學與工程學系所
引用: 參考文獻 [1] M. Cuviello, S. Dey, X. Bai, and Y. Zhao, “Fault modeling and simulation for crosstalk in system-on-chip interconnects”, in Proc. of ICCAD 1999, San Jose, CA, USA, pp. 297–303, 7–11 November. [2] M. Cuviello, S. Dey, X. Bai, and Y. Zhao, “Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects,” in 1999 Int. Conf. Computer-Aided Design, San Jose, CA, pp. 297–303, Nov. 1999. [3] M.R. Becer, D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov, and I.N. Hajj, “PostRoute Gate Sizing for Crosstalk Noise Reduction”, in Proc. Int’l Symp. Quality Electronic Design (ISQED), pp. 171-176, Mar. 2003. [4] F. Hasani and N. Masoumi, “Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization”, Des. and Tech. of Integr. Syst. in Nanoscale Era (DTIS), pp. 1 – 6, 2008. [5] L. Macchiarulo, E. Macii, and M. Poncino, “Wire Placement for Crosstalk Energy Minimization in Address Buses,” DATE’02, pp. 158–162, Mar. 2002. [6] C.J. Akl and M.A. Bayoumi, “Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion”, in Proc. Very Large Scale Inte. (VLSI) Sys., pp. 1230 – 1239, 2008. [7] R. Arunachalam, E. Acar, and S. Nassif, “Optimal shielding/spacing metrics for low power design,” in Proc. IEEE Symp. VLSI, pp. 167-172, Feb. 2003. [8] P. Gupta and A. B. Kahng, “Wire swizzling to reduce delay uncertainty due to capacitive coupling,” in Proc. Int. Conf. VLSI Des., pp. 441–445, Jan. 2004. [9] K. Hirose and H. Yassura, “A bus delay reduction technique considering crosstalk,” in Proc. Des. Autom. Test Eur. (DATE), pp.441–445, 2000. [10] A. B. Kahng, S. Muddu, E. Sarto, and R. Sharma, “Interconnect tuning strategies for high-performance ICs,” in Proc. Des. Autom. Test Eur. (DATE), pp. 471–478 1998. [11] Wen-Wen Hsieh, Po-Yuan Chen, and TingTing Hwang, “A bus architecture for crosstalk elimination in high performance processor design “ , Hardware/Software Code. and Syst. Synt., pp. 247 – 252, 2006. [12] Y. Cao, C. Hu, X. Huang, A. B. Kahng, S. Muddu, D. Stroobandt, and D. Sylvester, "Effects of global interconnect optimizations on performance estimation of deep submicron design", Proc. IEEE/ACM Int. Conf. Computer-Aided Design, pp.56 – 61, 2000. [13] D. Pamunuwa and H. Tenhunen, “Repeater insertion to minimise delay in coupled interconnects”, VLSI Design, pp. 513 – 517, 2001. [14] Narender Hanchate and Nagarajan Ranganathan, “Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory” IEEE Computer Society, 2006 IEEE [15] S. Khatri, A. Mehrotra, R. Brayton, and R. H. J. M. Otten, “A novel VLSI layout fabric for deep sub-micron applications”, in Proc. IEEE/ACM Des. Auto. Conf. (DAC), pp. 491 - 496, Jun.1999.
摘要: 在製程技術進步的發展下,晶片內相鄰導線之間的間距也越來越小,因耦合效應(coupling effect)導致導線之間的串音雜訊(crosstalk noise)干擾也趨於嚴重,雜訊干擾往往影響到訊號的完整性(SI),可能會使系統擷取到不正確的訊號,進而發生不可預期的錯誤。目前已有許多針對耦合效應產生的串音雜訊的相關研究方法,其方法都能有效的抑制雜訊的產生,但相對的也需要付出額外的成本,在考慮晶片面積的完整使用的條件下,[8]提出了解決雜訊干擾的方法,然而在考慮不同的電路模組後,仍有其改善的空間。 在本篇論文中,我們提出一個具有主動式回朔功能的電路,掛載在受到干擾的導線上,由於使用小面積的元件設計,可節省晶片的面積,並且能有效的抑制串音雜訊的產生。在六種不同的錯誤模型(Fault Models)中,我們提出的方法在考慮能量、功率消耗與漏電流的消耗上,能小幅度的優於[8]中使用的方法,並且能減低掛載額外電路後產生的負面影響,達到耗費小額成本,卻依舊能有效抑制串音雜訊的概念。
In the development of manufacture technology, the chip spacing between adjacent wires are also more closer, resulting in coupling between the wires caused by the crosstalk noise interference tends to be severe. The interference of noise often effect signal integrity, it may cause the chip does not have the correct signal, and thus unexpected error occurred. In this paper, we propose an enhanced driver (ED) that having self-tuning ability, and mounted in the interfered wire. The use of small areas of component design, it can save chip area, and can effectively reduce crosstalk noise. ED can be effectively used to optimize the results to reduce energy and power consumption and leakage current consumption. Otherwise ED can reduce the side effect that mounted another component on the wire. It has a concept that spending a small cost, but still can effectively reduce crosstalk noise.
URI: http://hdl.handle.net/11455/19786
Appears in Collections:資訊科學與工程學系所

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