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A Statistical Traffic Analysis for Path Selection in Networks on Chip
Networks on chip
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|摘要:||隨著半導體科技的進步，越來越多的矽智財核心可整合在晶片內。這種現象將導致晶片內的流量將越來越大量，所以傳統系統晶片(System on Chip，SoC)的匯流排架構(Bus architecture)將無法負荷此龐大的資料量。於是晶片網路 (Networks on Chip，NoC)的概念被視為解決未來系統晶片溝通量大量增加的方法。
Recently, following the development of semiconductor technology, there are more and more intellectual property(IP) cores that are integrated together in a chip. Hence, chip creates more communication traffic, so the traditional bus architecture of system-on-chip(SoC) cannot support the huge traffic. Networks on chip(NoC) has become one of the promising candidates to solve the large communication demands of SoC systems. Deadlock-free routing and efficient path selection strategy are critical factors for the performance of NoC. If we accurately estimate congestion of the network, the performance of path selection strategy is increased. The traditional method is to monitor the buffer utilization of router to determine the congestion situation, but there are two cases which cannot determine the congestion situation of NoC. In this paper, we present a path selection strategy that can more precisely estimate the network situation to avoid congestion nodes by using buffer utilization and analyzing the packet direction from the buffer of the router. The proposed selection strategy aims to choose the suitable channel that transmits the packet to the destination and considers transmission delay as less as possible. We also proposed a mathematical analysis to obtain the average transmission packet delay in non-saturated packet injection rate . Simulation results show the proposed strategy that improves odd-even routing and outperforms the average transmission packet delay of other path selection strategies on different traffic scenarios.
|Appears in Collections:||資訊科學與工程學系所|
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