Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/2979
標題: 利用有限元素法研究先進電晶體元件之通道應力分佈
Finite Element Method Investigation for Stress Distribution in Advanced Transistor Devices
作者: 林昆翰
Lin, Kun-Han
關鍵字: Finite Element Method
有限元素法
Stress Distribution
應力分佈
出版社: 光電工程研究所
引用: [1]半導體產業推動辦公室專刊NO.27,pp. 22,2007。 [2]林宏年、呂嘉裕、林鴻志、黃調元,「局部與全面形變矽通道(strained Si channel)互補式金氧半(CMOS)之材料、製程與元件特性分析(I)」,奈米通訊第十二卷第一期,pp. 44-45,民國94年2月。 [3]C. Gallon, G. Reimbold, G. Ghibaudo, R.A. Bianchi, R. Gwoziecki, “Electrical analysis of external mechanical stress effects in short channel MOSFETs on (0 0 1) silicon,” Solid-State Electronics, vol. 48, pp. 561-566, (2004). [4]S. Thompson et al., “A 90 nm Logic Technology Featuring 50nm Strained SiliconChannel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1 mm2 SRAM Cell,” IEDM Tech Dig. 61-64, (2002). [5]T. Ghani et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” IEDM Tech. Dig., 978 (2003). [6]Z. Krivokapic et al., “Locally Strained Ultra-Thin Channel 25nm Narrow FDSOI Devices with Metal Gate and Mesa Isolation,” IEDM Tech Dig.,pp.445-448, (2003). [7]V. Chan et al., “High Speed 45nm Gate Length CMOSFETs Integrated Into a 90nm Bulk Technology Incorporating Strain Engineering,” IEDM Tech Dig., pp.77-80, (2003). [8]C.-H. Ge et al., “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” IEDM Tech Dig., pp.73-76, (2003). [9]F.-L. Yang et al., “Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling,” Symp. VLSI Technology Dig., pp. 137-138, (2003). [10]T. Sanuki et al., “Scalability of Strained Silicon CMOSFET and High Drive Current Enhancement in the 40nm Gate Length Technology,” IEDM Tech Dig., pp.65-68, (2003). [11]K. Oda et al., “Novel Locally Strained ChannelTechnique for High Performance 55nm CMOS” IEDM Tech Dig., pp.27-30, (2002). [12]A. Shimizu et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancenient,” IEDM Tech Dig., pp.433-436, (2001). [13]K. Rim et al., “Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs,” VLSI Symposium , pg. 98-99, June (2002). [14]B. H. Lee, A. Mocuta, S. Bedell, H. Chen, D. Sadana, K. Rim, P. O''Neil, R. Mo, K. Chan, C. Cabral, C. Lavoie, D. Mocuta, A. Chakravarti, R. M. Mitchell, J. Mezzapelle, F. Jamin, M. Sendelbach, H. Kermel, M. Gribelyuk, A. Domenicucci, K. A. Jenkins, S. Narasimha, S. H. Ku, M. Ieong, I. Y. Yang, E. Leobandung, P. Agnello, W. Haensch, and J. Welser, “Performance enhancement on sub-70nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D”, in IEDM Tech. Dig., pp.946-948, December (2002). [15]K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carmthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, “Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs”, IEDM Tech. Digest , pp. 49-52, Dec (2003). [16]A.Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, F. Ootsuka, “Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement,” in IEDM Tech Dig., pp. 433–436,(2001). [17]G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., pp. 827–830, (1999). [18]T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass,T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry,A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith,K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEDM Tech Dig., pp. 978–980, (2003). [19]R.People, “Physics and applications of GexSi1−x/Si strained layer heterostructures,”IEEE J. Quantum Electron, vol. 22, pp. 1696–1710,Sept. (1986). [20]D.V. Lang, R. People, J.C. Bean, and A.M. Sergent, “Measurement of bandgap GexSi1−x/Si strained-layer heterostructures,” Appl. Phys. Lett.,vol. 47, no. 12, pp. 1333–1335, Dec. 15, (1985). [21]Nidhi Mohta and Scott E. Thompson, “Mobility Enhancement: The Next Vector to Extend Moore’s Law”, IEEE Circuits& Devices Magazine , (2005). [22]R. W. Olesinski and G. J. Abbaschian, “The Ge-Si (germanium-silicon) system,” Bull. Alloy Phase Diagrams, 5(2), p.180, (1984). [23]T. Ghani, M. Armstrong, C. Auth, M. Bost, etc., “A 90nm High Volume Manufacturing Lobic Technology Freaturing Novel 45nm Gate Length Strained CMOS Transistors,” intel. [24]Y. Toivola, J. Thurn, and R. F. Cook, “Influence of deposition conditions on mechanical properties of low-pressure chemical vapor deposited low-stress silicon nitride films,” Appl. Phys. J., 94, pp. 6915-6922 (2003). [25]Chee Wee Liu, S.Maikap, and C.-Y. Yu, “Mobility-Enhancement Technologies”, IEEE Circuits& Devices Magazine , (2005). [26]T. Benabbas, P. Francois, Y. Androussi, and A. Lefebvre, ”Stress relaxation in highly strained InAs/GaAs structures as studied by finite element analysis and transmission electron microscopy,” Appl. Phys. J., 80, pp. 2763-2767 (1996). [27]宋裕祺、蘇進國、張荻薇,「有限元素法在鋼斜張橋結構分析之應用」 “Applications of Finite Element Method on Structural Analysis of Steel Cable-Stayed Bridges”,中日「鋼結構工程」研討會,Tainan,Taiwan,(2007)。 [28]賴育良、林啟豪、謝忠祐,「ANSYS電腦輔助工程分析」,儒林圖書有限公司,台北,pp. 1-5~1-7,(2002)。 [29]劉晉奇,電腦輔助工程分析入門:ANSYS速學,五南圖書出版股份有限公司,(2009)。 [30]賴育良、林啟豪、謝忠祐,「ANSYS電腦輔助工程分析」,儒林圖書有限公司,台北,(2001) 。 [31]陳建良,國立中央大學機械工程研究所,「鐵路客車車廂結構體之應力與疲 勞壽命分析」碩士論文,pp. 5,(2000)。 [32]Sentaurus user manual [33]G. H. Wang et al., “Silicon-Germanium-Tin (SiGeSn) Source and Drain Stressors formed by Sn Implant and Laser Annealing for Strained Silicon-Germanifum Channel P-MOSFETs,” IEDM Tech Dig.131-134, (2007). [34]M.H. Lee, P.S. Chen, W.-C. Hua, C.-Y. Yu, Y.-C. Lee, S. Maikap, Y.M.Hsu, C.W. Liu, S.C. Lu, W.-Y. Hsieh, and M.-J. Tsai, “The noise characteristics of strained-Si MOSFETs,” in Proc. Int. SiGe Technol. And Device Meet. (ISTDM), Frankfurt, Germany, pp. 87–88, (2004). [35]M.H. Lee, P.S. Chen, W.-C. Hua, C.-Y. Yu, Y.T. Tseng, S. Maikap, Y.M. Hsu, C.W. Liu, S.C. Lu, W.-Y. Hsieh, and M.J. Tsai, “Comprehensive low-frequency and RF noise characteristics in strained-Si NMOSFETs,” in IEDM Tech. Dig., pp. 69–72, (2003). [36]B. Vincent, Y. Shimura, S. Takeuchi, T. Nishimura, G. Eneman, A. Firrincieli, J. Demeulemeester, A. Vantomme, T. Clarysse, O. Nakatsuka, S. Zaima, J. Dekoster, M. Caymax, R. Loo, Microelectronic Engineering, Vol. 88, pp. 342-346, (2011). [37]B.-F. Hsieh and S. T. “ChangImpact of Strain Engineering on Nanoscale Ge PMOSFET ” SNDT, (2012). [38]M. V. Fischetti, S. E. Laux, Physical Review B, Vol, 48, pp.2244-2274 ,(1993). [39]R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar, and M. Radosavljevic, “Application of High- k Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology,” Microelectronic Engineering, vol. 80, pp. 1-6, (2005). [40]M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit and R. Chau, “Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (< 2 μm) Composite Buffer Architecture for High-Speed and Low-voltage ( 0.5V) Logic Applications,” International Electron Devices Meeting, Tech Dig., pp. 625-28, (2007). [41]S. Suthram, P. Majhi, G. Sun, P. Kalra, H. R. Harris, K. J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B.J. Cho, M. M. Hussain, C. Smith, S. Banerjee, W. Tsai, S. E. Thompson, H. H. Tseng, R. Jammy , “High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node,” International Electron Devices Meeting Tech Dig., pp. 727-30, (2007). [42]S. Suthram, Y. Sun, P. Majhi, I. Ok, H. Kim, H. R. Harris, N. Goel, S. Parthasarathy, A. Koehler, T. Acosta, T. Nishida, H. H. Tseng, W. Tsai, J. Lee, R. Jammy and S. E. Thompson, “Strain Additivity in III-V Channels for CMOSFETs beyond 22nm Technology Node,” Symposia on VLSI Tech Dig., pp. 182-83, (2008). [43]H. C. Chin, X. Gong, X. Liu, Z. Lin, Y.C Yeo, “Strained In0.53Ga0.47As n-MOSFETs: Performance Boost with in-situ Doped Lattice-Mismatched Source/Drain Stressors and Interface Engineering,” Symposia on VLSI Tech Dig. pp. 244-45, (2009). [44]Aneesh Nainani, Jung YumJoel Barnett, Richard Hill, Niti Goel, Jeff Huang, Prashant Majhi, Raj Jammy, and Krishna C. Krishna C. Saraswat, “Study of piezoresistance under unixial stress for technologically relevant III-V semiconductors using wafer bending experiments,” APPLIED PHYSICS LETTERS 96, 242110, (2010). [45]Sarah H. Olsen, Anthony G. O’Neill, Sanatan Chattopadhyay, Luke S. Driscoll, K. S. K. Kwa, D. J. Norris, A. G. Cullis, and Douglas J. Paul, “Study of Single- and Dual-Channel Designs for High-Performance Strained-Si-SiGe n-MOSFETs,” IEEE Trans. Electron Devices, vol. 51, pp.1245-1253, July (2004). [46]D. Zhang et al., “Embedded SiGe S/D PMOS on Thin Body SOI Substrate with Drive Current Enhancement,” Symp. VLSI Technology Dig., 26 (2005). [47]Ling Xia1 et al, “Performance Enhancement of P-channel InGaAs Quantum-well FETs by Superposition of Process-induced Uniaxial Strain and Epitaxially-grown Biaxial Strain,”Electron Devices Meeting (IEDM),IEEE,pg13.5.1-13.5.4, (2011). [48]T. O’Regan, M. Fischetti and J Comput, Electron, “Electron mobility in silicon and germanium inversion layers: The role of remote phonon scattering,” vol. 6, pp. 81-84, (2007). [49]H. J. G. Meijer, Polder, Physica, “Extending continuous versus discontinuous conditioned stimuli before versus after unconditioned stimuli,” vol. 19, pp. 255-264, (1993). [50]Yan Zhang, “Hole Mobility in Strained Ge and III-V P-channel Inversion Layers with Self-consistent Valence Subband Structure and High-k Insulators,” University of Massachusetts, Dissertations and Theses, (2010). [51]Synopsys Sentaurus201003 user Manual. [52]C. Droz, E. V.Sauvain, J. Bailat, L. Feitknecht, J. Meier, X. Niquille and A. Shah, “ELECTRICAL AND MICROSTRUCTURAL CHARACTERISATION OF MICROCRYSTALLINE SILICON LAYERS AND SOLAR CELLS,” Proceedings of 3rd World Conference on Photovoltaic Energy Conversion, Osaka. Japan, May 11-18, (2003). [53]C. C. Lee, J. Huang, S. T. Chang and W. C. Wang, “Impact of channel width and dummy length on performance enhancement in p-type metal oxide semiconductor field effect transistor with a silicon-germanium alloy stressor,” Journal of Vacuum Science and Technology A, vol. 27, issue 3, pp. 1256,(2009). [54]Sentaurus201003 SDEVICE manual.
摘要: In this thesis, we use ANSYS simulator based on finite element method to study the stress distribution in the channel region of transistor device. Two types of stressors, namely SiGe S/D stressors and CESL, are investigated in this work. We study the impact of process parameters, such as initial stress of SiN-capping layer, S/D stressor due to lattice mismatch between S/D region and channel, channel width, and gate length on the stress distribution in the channel of transistor device.
本研究以ANSYS為模擬器,利用有限元素法來模擬3-D 電晶體元件之通道應力分佈。本研究主要探討二種應力來源,一為源/汲極(S/D)與通道間之晶格不匹配產生之應力源,另一為氮化矽應力源(CESL)。 本論文研究各種製程參數包括具初始應力氮化矽層、由源/汲極材料與通道材料晶格不匹配造成之源/汲極應力源、通道寬度、閘極長度對電晶體元件通道應力分佈之影響。
URI: http://hdl.handle.net/11455/2979
其他識別: U0005-2706201212440900
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2706201212440900
Appears in Collections:光電工程研究所

文件中的檔案:

取得全文請前往華藝線上圖書館



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.