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標題: 填充矽通孔之新穎電鍍鎳鎢合金配方
A Novel Nickel-Tungsten Alloy Plating Formula for Filling Through Silicon Vias
作者: 黃馨嫚
Huang, Hsin-Man
關鍵字: 填充矽通孔
Through Silicon Vias
Nickel-Tungsten Alloys
出版社: 化學工程學系所
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摘要: 摘要 三維晶片堆疊技術是近年來微電子領域中最受矚目的研究課題與發展,其中IC晶片堆疊中的矽通孔是連接傳訊的關鍵角色,其主要優點在於可縮短訊號傳遞路徑、縮小晶片所佔之空間及減少訊號延遲等特點,符合現今電子產品輕薄短小的趨勢。電化學沉積在矽通孔技術中扮演一重要角色,其中金屬銅沉積部分已普遍使用於三維堆疊領域。 在電化學沉積過程中,普遍使用鈍態金屬作為導體,如:銅、銀或金等類型。由於銅沉積技術已發展至相當成熟之程度,因此近年來將此超級填充方式延伸至磁性材質,如:鐵、鈷、鎳及鎢等金屬。近年由於鎢金屬抗腐蝕與低熱膨脹係數之特性所以備受矚目,但由於鎢金屬是以WO42-狀態存在於水溶液中,無法單獨進行電化學沉積,須以合金金屬型式進行電鍍沉積;其中以鎳鎢之合金搭配最具潛力,可有效提升鍍層之硬度、耐腐蝕、抗酸鹼及熱膨脹係數低等優勢,同時與避免金屬擴散之阻障層金屬材質相同,可取代原有之阻障層與晶種層直接電鍍,完成鎳鎢合金矽通孔。因此本論文致力於此金屬材質之矽通孔沉積研究,找尋其適用之合金比例、電流效率及添加劑等沉積條件。 本實驗主要以硫酸鎳與鎢酸鈉為鎳鎢合金電鍍液成份,其中以檸檬酸作為螯合劑。藉由改變添加劑、電流密度等不同的實驗變因,進而探討對於填充矽通孔之影響。由實驗結果明顯發現此鍍液易形成共形沈積的填孔模式,需搭配其他的添加劑來加以改善其沈積方式,以實際電鍍及多項的電化學分析方式,試驗不同的添加劑、電流密度及攪拌速率等變因,探討其對於填孔機制及鎳鎢含量之影響。
Abstract Three-dimensional (3D) chip stacking is a major focus in recent research and development of microelectronics, MEMS, and MOEMS technology. Through silicon vias (TSV) play a key role in IC chip stacking connections. A main advantage of TSV is the shortest chip-to-chip vertical interconnection, which allows for size reduction of the chip and reducing signal transmission delay. Electrodeposition plays an important role in TSV development, especially copper electrodeposition, which is a critical technology and generally used in 3D chip packaging. In TSV technology, the thermo-mechanical fatigue may lead to the TSV interconnects failures because the coefficient of thermal expansion (CTE) of copper is much higher than that of silicon. The package materials with different CTEs will induce large stresses at the interfaces. In order to overcome this problem, we choose tungsten to substitute copper. However, tungsten cannot be directly plated in an aqueous electrolytes, it can be co-deposited with iron group metals. Nickel-tungsten alloy has excellent corrosion resistance, wear resistance and mechanical strength, which is a favorable candidate. Traditional process for TSV is dry process that includes the following step: (1) formation of vias by reactive ion etching; (2) formation of a SiO2 isolation layer; (3) deposition of a TiN barrier layer and a copper seed layer; (4) electrodeposition of copper inside the via. In our research, we reduce the procedure of TSV using the wet process to substitute barrier and seed layer with CoWP, and electrodeposition with Ni-W alloy to make a copper-free process. In other words, a copper-free TSV with simplified processing steps is fabricated leading to lower fabrication cost, moreover, a low-stress TSV filled with low CTE metals is also fabricated to improve the thermo-mechanical fatigue of TSV leading to better package reliability. The Ni-W alloy was plated using NiSO4 and NaWO4 electrolytes; the additives included suppressor, accelerator, and surfactant. This Ni-W plating formula can achieve bottom-up filling of TSV with an aspect of 3.2 and a diameter of 20μm.
其他識別: U0005-2407201221200300
Appears in Collections:化學工程學系所



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