Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/3542
標題: Electroless Deposition of Barrier and Seed Layersof Through Silicon Via
以無電鍍法沉積矽通孔之阻障層與導電層
作者: 周嘉珮
Chou, Chia-Pei
關鍵字: electroless deposition
無電鍍
CoWP
TSV
wet process
鈷鎢磷
矽通孔
全濕製程
出版社: 化學工程學系所
摘要: The development of science is constantly progressing. The densification of electronic components continuously increases. In order to meet this general demand, many new three-dimensional (3D) electronic packaging technologies are now emerging, especially with through silicon via (TSV) technology. Before TSV formation by copper plating can occur, it must have a good barrier to prevent copper diffusion into silicon and also a conducting layer to enable the copper plating. Although TaN is currently the best material to use as a barrier layer, it still has several drawbacks. First, because TaN is comprised of several equilibrium phases and metastable structures, changing the atomic ratio can influence the film structure. Second, TaN-based films can only be deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD) methods, which are high cost and require special conditions such as a vacuum and high temperatures. Furthermore, for high aspect ratio vias and trenches, PVD and CVD are unable to create a uniform conformal structure. The conducting layer is also deposited by PVD or CVD. If the seed layer coverage is not complete, the via filling process easily fails. In this situation, another process is needed to resolve this problem. To resolve these issues, cobalt-tungsten-phosphorus (CoWP) was chosen as the barrier layer. According to the previous study, CoWP film was needed in the annealing process to help remove defects. For this high temperature process, the thermal budget needed to be considered. In order to simplify the process, a method of chemical treatment was examined. This work used an overall wet process to carry out TSV metallization, using CoWP as the barrier layer and copper as the seed layer. First, the wafer was prepared with a surface pretreatment of (3-Aminopropyl)trimethoxysilane(APTMS) via silanization, follow by adsorption of Pd+2 onto the surface. These deposition points then acted as the nucleation sites for electroless deposition of CoWP. During this process, the organic additive UPS was added to modify the surface morphology of the film with only 0.1 ppm UPS, the film become denser and helped to eliminate defects. The CoWP film can effectively block copper diffusion and has good barrier ability even after annealing at 600℃ for 30 minutes. Copper nanoparticles (CNPs) were then deposited on CoWP through chemical grafting. The CNPs became the nucleation sites for copper electroless deposition. Properties such as elemental makeup, surface morphology, and thermal stability was examined and investigated by various instruments. Using this process, an aspect ratio of 6 was achieved.
隨著時代的演進與科技的發展,電子元件在單位面積上的密度大幅增加,因此許多新穎的封裝型式被開發出來,目前最被看好的3D封裝技術是利用矽通孔做為晶片互相連接的通道,但在電鍍填孔前,必須先沉積一層阻障層與導電層,目前最常使用的阻障層材料為氮化鉭,但是使用此金屬當阻障材料有以下的缺點 : 這兩種金屬存在很多平衡相以及較不穩定,很容易受到外界環境的影響而改變結構,此外,必須藉由化學氣相沉積或物理氣相沉積才有辦法沉積此薄膜,這些設備昂貴且需要在高真空系統與高溫下進行,並且若是用於高深寬比的矽通孔,均一性將大幅下降;而導電層大多是使用銅,也是藉由化學氣相沉積或物理氣相沉積,若是均一性不佳,將導致後續電鍍填孔時,孔底有孔洞的產生,因此為了改善此問題,必須開發出新的製程;此外,吾人選擇以CoWP薄膜作為阻障層材料,但若是要得到一表面無缺陷,完整的薄膜表面,必須先經過高溫熱處理,才層消除表面的缺陷,此高溫製程雖可有效的改善薄膜表面形態,提升應有的阻障特性,但其加熱的步驟,則需考慮到熱預算,因此希望以化學方法來改善薄膜表面形態。 利用全濕製程方式,將矽通孔進行金屬化,阻障層材料為鈷-鎢-磷,導電層材料為銅。研究首先以平面基材來探討,選用三甲基矽烷進行化學接枝,後續再以鈀活化基材,做為催化無電鍍鈷-鎢-磷的晶種層,並且添加UPS改善薄膜表面型態,在僅加入0.1ppm時就能夠有效的改善,使得鈷-鎢-磷薄膜較緻密且連續,;此外,後續再以化學接枝法沉積奈米銅做為催化觸媒,以利後續無電鍍銅的生成。吾人藉由場發射掃描式電子顯微鏡觀察阻障層與導電層的表面形態,並且利用電子能譜儀鑑定每一步驟對基材表面金屬化的影響,及利用歐傑電子能譜儀以縱深分析量測鈷-鎢-磷對銅的阻障能力,在經過600℃退火30分鐘後,依然保有良好的阻障性質,後續將全濕製程運用在矽通孔上,進行金屬化製程,最後吾人成功地將孔徑10微米、孔深60微米,深寬比為6的孔,以無空洞或隙縫之結構完整填充。
URI: http://hdl.handle.net/11455/3542
Appears in Collections:化學工程學系所

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