Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/37678
標題: Test and diagnosis of faulty logic blocks in FPGAs
作者: Wang, S.J.
王行健
Tsai, T.M.
期刊/報告no:: Iee Proceedings-Computers and Digital Techniques, Volume 146, Issue 2, Page(s) 100-106.
摘要: Field programmable gate arrays (FPGAs) have been used in many areas of digital design. Because FPGAs are programmable, faults in them can be easily tolerated once fault sites are located. However, diagnosis of faults in FPGA has not yet been explored by researchers. A new methodology for the testing and diagnosis of faults in FPGAs is presented, based on built-in self-test. The proposed method imposes no hardware overhead, and requires minimal support from external test equipment. Test time depends only on the number of faults, and is independent of the chip size. With the help of this technique, chips with faults can still be used. As a result, the chip yield can be improved and chip cost is reduced. This method can also be used in fault-tolerant systems, in which a good functional circuit can still be mapped to a. FPGA with faulty elements, as long as the fault sites are known.
URI: http://hdl.handle.net/11455/37678
ISSN: 1350-2387
文章連結: http://dx.doi.org/10.1049/ip-cdt:19990532
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