Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/37691
標題: Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction
作者: Tsai, P.C.
王行健
Wang, S.J.
關鍵字: circuits
algorithms
placement
power
期刊/報告no:: Iet Computers and Digital Techniques, Volume 2, Issue 6, Page(s) 434-444.
摘要: Broadcast-based test compression techniques can reduce both test data and test time. However, the success of such methods heavily depends on the percentage of test patterns that can be broadcasted. In this paper, we first conduct a quantitative analysis that shows the simple broadcast architecture that cannot achieve good test time/data compression even under a test set with very high level of don't care bits. A multi-mode-segmented scan test architecture (MSSA) is then presented to solve the problem of low broadcast rate. Three operation modes are supported in this architecture: broadcast, multicast and serial. As a result, improved test data compression is achievable with limited hardware overhead, as serial-mode operations are largely eliminated. An algorithm for the two-way partitions of the scan segments is proposed to construct multicast mode configurations. Finally, we present a layout-aware scan chain ordering method to further improve test compression. The problem of ordering scan cells in multiple scan chains is mapped to a constrained standard cell placement problem in physical synthesis, and the simulated annealing method is used to solve the problem. The routing length of the scan chains are also taken into account in the ordering process.
URI: http://hdl.handle.net/11455/37691
ISSN: 1751-8601
文章連結: http://dx.doi.org/10.1049/iet-cdt:20070115
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