Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/37697
標題: Testability improvement by branch point control for conditional statements with multiple branches
作者: Wang, S.J.
王行健
Lien, C.C.
關鍵字: VLSI
high-level test synthesis
behavioral statement
BIST
conditional
branch
期刊/報告no:: Journal of Information Science and Engineering, Volume 16, Issue 5, Page(s) 719-731.
摘要: High-level test synthesis (HLTS) methodologies have attracted much many research interest in recent years as digital design has moved to higher levels of abstraction. Conditional statements in behavioral descriptions tend to produce test-ability problems and have to be taken care of in the early stage of the design cycle. In this paper, we present an HLTS methodology for the Built-in Self-Test (BIST) environment. Our methods modify conditional case statements in the original design so as to control the number of test patterns applied to modules being tested. As a result, the number of required test patterns can be greatly reduced. This method is especially useful when there is a wide variance in the number of random test patterns required for functional units. Experimental results show that our methods achieve a high degree of fault coverage with a much smaller number of test patterns while the area and time overheads are negligible.
URI: http://hdl.handle.net/11455/37697
ISSN: 1016-2364
Appears in Collections:資訊科學與工程學系所

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