Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/3773
標題: 填充矽通孔之新穎電鍍銅配方
A Novel Copper Electroplating Formula for Filling Through Silicon Vias
作者: 陳偉翔
Chen, Wei-Hsiang
關鍵字: eletroplating
電鍍
through silicon vias
copper deposition
3D chip stacking
interconection
矽通孔
銅導線
沉積銅
三維晶片堆疊
出版社: 化學工程學系所
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摘要: 為了追求日新月異的科技,將產品微小化、製作成本降低以及效能提升持續在進行,相關的研究也因此而持續在發展,能將以上目標完成的3D晶片堆疊技術因此而被開發。本論文的研究目的是希望能將在3D晶片堆疊技術不可或缺的矽通孔(Through Silicon Vias, TSV)以電鍍的方式完全充塞銅在其中,促使3D晶片堆疊技術的開發。 為了填充銅於高深寬比的矽通孔內,以往用在印刷電路板的電鍍添加劑已不堪使用,因此吾人先利用電化學分析方法初步挑選出一些新穎之電鍍添加劑,將其分別以單劑與多劑的電鍍填孔方試進行電鍍,找出其適當的電鍍方式及參數。吾人分別找出適用於多劑的平整劑並命名為TTC,而適用於單劑的平整劑為TV。當TTC運用於多劑配方電鍍填孔,除了能使孔完全充塞銅,更能在填孔的同時使銅以平台方式沉積於孔內,降低孔洞與縫隙的產生。經過篩選與測試後吾人發現TV適合以單劑填孔電鍍方式使銅沉積於孔內,除此之外也發現使用此配方能造成板面不沉積銅,降低後續利用化學機械研磨(Chemical Mechanical Polishing, CMP)去除的負擔並降低製作成本。 在3D晶片堆疊技術中有各個製程,前端製程的好壞會影響後續步驟,而在電鍍前端的是晶種層的沉積,在本論文中的實驗晶圓皆以濺鍍方式沉積晶種銅層使矽通孔具有導電性,但其是有缺陷的,其優缺將嚴重影響後續電鍍製程,吾人發現一個可以延伸晶種層連續性的配方,可以將孔徑20μm孔深70μm深寬比達3.5經過濺鍍的矽通孔完全被銅所覆蓋,並整合TV單劑電鍍填孔方式完成孔底上移的目標。
The development of modern science and technology proceeds quicker and quicker. Three-dimensional (3D) integration of chips is fast growing to carry out high-speed performance and high-density packaging. 3D integration uses through-silicon-vias (TSVs) to interconnect multiple active circuit layer in a single chip, that performs high density interconnects with a small form factor. This thesis achieves void-free TSV filling using electrochemical deposition (ECD) of copper, because a void formed in the TSV may cause serious reliability issues. Since the aspect ratio of the TSV is much higher than that of the vias of printed circuit boards (PCBs), a common copper plating formula for PCBs cannot fully fill the TSV with copper deposit. In this thesis, some novel organic additives were screened by chronopotentiometry to be levelers. Electroanalytical measurements and feature-filling experiments were carried out to study the effect of these additives. Copper electroplating formulas with multi-component and with single component for TSV filling were developed. TTC is a new additive, which is appropriate for TSV filling in multi-component method. A trapezium-type profile of the top copper deposit in the filled TSV was achievable using the plating formula with TTC. This plating process can make sure of no void and seam formation during plating. TV was a novel additive for filling TSV in a single component system. Surprisingly, the thickness of copper on the wafer surface was a constant during the plating process, indicating that the copper deposition is highly selective. The high selectivity of copper fill greatly reduces the loading of chemical mechanical polishing (CMP) and saves the process time of TSV. The insulating layer, barrier layer and copper seed layer were formed inside the TSV before copper electrodeposition. However, the step coverage of sputtered copper seed layer was not good enough. A void-free filling of the TSV is not only achieved by an excellent plating formula but also by good continuity and conformality of the seed layer. The thickness of the seed layer coated on the via wall has significant effect on the TSV filling. If the seed layer is not continuous, then a void-free filling of the TSV is not achievable. In this work, we developed another plating formula to repair the discontinuous seed layer rendering it to be continuous and conformal. Thus, the TSV with a high aspect ratio were fully filled after repairing the seed layer using the special plating formula.
URI: http://hdl.handle.net/11455/3773
其他識別: U0005-2407200915511700
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2407200915511700
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