請用此 Handle URI 來引用此文件: http://hdl.handle.net/11455/38463
標題: Number of Vias: A Control Parameter for Global Wiring of High Density Chips
作者: D.T.Lee
S.J.Hong
C.K.Wong
摘要: In integrated circuits, components are frequently interconnected by horizontal and vertical wires in respective wiring planes whether on chip, card, or board. The wire changes direction through “vias” that connect the orthogonal wiring planes. Because of technology constraints, the arrangement of vias must conform with certain neighborhood restrictions. We present results on the guaranteed minimum number and maximum possible number of vias in a given wiring cell for various technology constraints. These numbers provide an early means of control on global wiring routes to further the success of the exact embedding process that follows global wiring.
URI: http://hdl.handle.net/11455/38463
ISSN: 0018-8646
顯示於類別:資訊科學與工程學系所

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