Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/40016
標題: Turn-Around Phenomenon in the Degradation Trend of n-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors under DC Bias Stress
作者: Liu, H.W.
汪芳興
Chiou, S.M.
Wang, F.H.
劉漢文
期刊/報告no:: Japanese Journal of Applied Physics, Volume 49, Issue 7.
摘要: In this research, the instability of n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) is investigated under DC bias stress and a unique phenomenon is observed. At a large gate stressing voltage and simultaneous low to moderate drain biasing voltages operating in a linear region, a turn-around phenomenon is observed in the on-current (I(on)) degradation trend of the TFT characteristics, resulting from the increase in maximum transconductance (G(m,max)). However, under a larger drain stressing voltage, the turn-around phenomenon of the I(on) degradation trend is observed to disappear owing to the extensive increases in threshold voltage (V(th)) and trap state density (N(trap)) in a channel, which cause the TFTs to deteriorate monotonically. (C) 2010 The Japan Society of Applied Physics
URI: http://hdl.handle.net/11455/40016
ISSN: 0021-4922
文章連結: http://dx.doi.org/10.1143/jjap.49.074103
Appears in Collections:光電工程研究所

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