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dc.contributor.authorDow, Wei-Pingen_US
dc.contributor.authorLu, Chun-Weien_US
dc.contributor.authorLin, Jing-Yuanen_US
dc.contributor.authorHsu, Fu-Chiangen_US
dc.contributor.otherNational Chung Hsing University,Department of Chemical Engineeringen_US
dc.description.abstractIn this work, a copper plating formula that can directly and selectively fill the through silicon holes (TSHs) for 3D chip stacking packaging was developed. The copper plating technology reduced and simplified the process steps for fabricating through silicon vias (TSVs) and TSHs. The highly selectivity of copper fill in the TSHs also reduced the manufacture cost of 3D chip stacking packaging, because the copper plating technology reduced the loading of a post-copper chemical mechanical polishing (CMP) and did not need a post-thermal annealing treatment. The copper plating formula was very simple, just containing single organic additive.en_US
dc.publisherThe Electrochemical Societyen_US
dc.relationElectrochemical and Solid-State Letters, Volume 14, Issue 6, Page(s) D63-D67.en_US
dc.titleHighly Selective Cu Electrodeposition for Filling Through Silicon Holesen_US
dc.typeJournal Articlezh_TW
dc.contributor.catalogerMiao-zhen Luoen_US
Appears in Collections:化學工程學系所


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