Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/44203
標題: A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement
作者: Lin, W.L.
林維亮
Cheng, W.C.
Wu, C.H.
Wu, H.M.
Wu, C.Y.
Ho, K.H.
Chan, C.A.
關鍵字: Analog circuits
analog integrated circuits (IC)
education
layout
measurement
期刊/報告no:: Ieee Transactions on Education, Volume 53, Issue 2, Page(s) 282-287.
摘要: This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within one semester, and the grading cycle in the most recent offering of the course extended from September 2007 to February 2008, when there were 10 students enrolled. The manufacturer's shuttle cycle is 3.5 months. Most students in the course have only a college-level electronics background. The manufacturing process is Taiwan Semiconductor Manufacturing Company's (TSMC) 0.35 mu m CMOS Mixed-Signal 2P4M Polycide 3.3/5 V. The three successful chips consist of a voltage controlled oscillator, a high-performance differential amplifier, and a temperature-independent voltage reference generator. Section VI describes assessment and student feedback as well as proposed course improvement.
URI: http://hdl.handle.net/11455/44203
ISSN: 0018-9359
文章連結: http://dx.doi.org/10.1109/te.2009.2015654
Appears in Collections:電機工程學系所

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