Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/44238
標題: DESIGN AND VERIFICATION OF HIGH-THROUGHPUT IEEE 802.11 MAC-LAYER HARDWARE IP WITH FPGA PLATFORM
作者: Yang, Z.H.
范志鵬
Chen, Y.T.
Fan, C.P.
關鍵字: MAC-layer design
low latency
high throughput
FPGA verification
期刊/報告no:: Journal of the Chinese Institute of Engineers, Volume 33, Issue 4, Page(s) 551-562.
摘要: The development of a high-throughput and low-cost medium access control (MAC) layer design is a very important issue for wireless local area network (WLAN) communication. In this paper, the proposed MAC-layer hardware architecture is simplified by using a small number of finite state machines (FSMs) and a low-latency parallel processing architecture. The FSMs on both the transmitter (TX) and receiver (RX) sides can be operated at low power. In the MAC-layer receiver, an efficient low-complexity timestamp controller is proposed for fast timing synchronization. We implement the distributed coordination function (DCF) of the MAC protocol in IEEE 802.11a/b/g standards within the ad-hoc configuration. The proposed MAC-layer hardware is implemented with Xilinx XC4VLX60 FPGA, the hardware area needs 5944 slices, and the effective throughput is 147.6 Mbps. With TSMC 0.18 mu m CMOS process, the effective throughput at the maximum working frequency 83.3 MHz is 299.88 Mbps, which is larger than the standard IEEE 802.11 g requirement, i.e. 54 Mbps.
URI: http://hdl.handle.net/11455/44238
ISSN: 0253-3839
文章連結: http://dx.doi.org/10.1080/02533839.2010.9671643
Appears in Collections:電機工程學系所

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