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標題: A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications
作者: Tsai, M.T.
Yang, C.Y.
關鍵字: Frequency synthesizer
Phase-locked loop
Time-to-voltage converter
Fast locking
Voltage-controlled oscillator
Phase alignment
cmos pll
期刊/報告no:: Analog Integrated Circuits and Signal Processing, Volume 64, Issue 1, Page(s) 69-79.
摘要: In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-mu m CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of -106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 mu s and consume 39 mW from a 1.2-V power supply.
ISSN: 0925-1030
Appears in Collections:電機工程學系所



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