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標題: A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers
作者: Yang, C.Y.
關鍵字: frequency synthesizers
high-speed dynamic circuits
logic flip-flops
multi-modulus dividers
phase-locked loops
dual-modulus prescaler
dynamic flip-flops
期刊/報告no:: Analog Integrated Circuits and Signal Processing, Volume 55, Issue 2, Page(s) 155-162.
摘要: A high-frequency divide-by-256-271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-mu m CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.
ISSN: 0925-1030
Appears in Collections:電機工程學系所



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