Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/44508
標題: A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology
作者: Yang, C.Y.
楊清淵
Chang, C.H.
Wong, W.G.
關鍵字: Fractional divider
fractional-N phase-locked loop (PLL)
multiphase
signals
phase interpolation
spread-spectrum clock generation (SSCG)
Delta - Sigma modulator
cmos
modulation
noise
vco
期刊/報告no:: Ieee Transactions on Circuits and Systems I-Regular Papers, Volume 56, Issue 1, Page(s) 51-59.
摘要: A triangular-modulated spread-spectrum clock generator using a Delta - Sigma-modulated fractional-N phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased Delta - Sigma operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of +/- 0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies 950 x 850 mu m(2) in 0.18-mu m CMOS process and consumes 36 mW.
URI: http://hdl.handle.net/11455/44508
ISSN: 1549-8328
文章連結: http://dx.doi.org/10.1109/tcsi.2008.926975
Appears in Collections:電機工程學系所

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