請用此 Handle URI 來引用此文件: http://hdl.handle.net/11455/44510
標題: A PWM and PAM signaling hybrid technology for serial-link transceivers
作者: Yang, C.Y.
楊清淵
Lee, Y.
關鍵字: chip-to-chip communication
clock recovery
intersymbol interference
(ISI)
pulse-amplitude modulation (PAM)
pulse-width modulation (PWM)
serial link
as-memory
low-power
cmos
modulation
circuits
期刊/報告no:: Ieee Transactions on Instrumentation and Measurement, Volume 57, Issue 5, Page(s) 1058-1070.
摘要: A 1-Gb/s 0.18-mu m CMOS serial-link transceiver-using multilevel pulse-width and pulse-amplitude modulation (PWAM) signaling and a pre-emphasis technique is presented. Based on the PWAM technique, the transmit signaling is implemented to effectively, push high data rates through bandwidth-limited channels. The clock is implicitly embedded in the 4-bit data stream, and the associated overhead needed in the clock-and-data recovery circuitry can be mitigated. In addition, the pin count can be reduced by transferring the data channels and the clock channel over a single transmitted channel. The recovered clock has an rms jitter of 5.9 ps at 250 MHz, and the retimed data have an rms jitter of 13.7 ps at 250 Mb/s. The occupied die area is 1.65 x 1.40 mm(2). The transmitter and receiver power consumption is 86 and 45 mW, respectively.
URI: http://hdl.handle.net/11455/44510
ISSN: 0018-9456
文章連結: http://dx.doi.org/10.1109/tim.2007.915134
顯示於類別:電機工程學系所

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