Please use this identifier to cite or link to this item:
標題: A 1.25-Gb/s burst-mode half-rate clock and data recovery circuit using realigned oscillation
作者: Yang, C.Y.
Lin, J.M.
關鍵字: burst-mode CDR
clock recovery
phase-locked loop
realigned oscillation
期刊/報告no:: Ieice Transactions on Electronics, Volume E90C, Issue 1, Page(s) 196-200.
摘要: In this letter, a 1.25-Gb/s 0.18-mu m CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4 x 1.4 mm(2), and power consumption is 32 mW under a 1.8-V supply voltage.
ISSN: 0916-8524
Appears in Collections:電機工程學系所



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.