Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/44517
標題: A 3.2-GHz down-spread spectrum clock generator using a nested fractional topology
作者: Yang, C.Y.
楊清淵
Chang, C.H.
Wong, W.G.
關鍵字: spread spectrum clock generation
fractional phase-locked loop
delay-locked loop
phase compensation
fractional divider
sigma-delta modulator
emi reduction
pll
期刊/報告no:: Ieice Transactions on Fundamentals of Electronics Communications and Computer Sciences, Volume E91A, Issue 2, Page(s) 497-503.
摘要: A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N-1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 x 1.4 mm(2) in a 0.18-mu m CMOS process and consumes 52 row.
URI: http://hdl.handle.net/11455/44517
ISSN: 0916-8508
文章連結: http://dx.doi.org/10.1093/ietfec/e91-a.2.497
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