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標題: Design of a 20-GHz Low-Noise Phase-Locked Loop with a Varactorless VCO
作者: 楊清淵
關鍵字: 鎖相迴路
phase-locked loop (PLL)
frequency synthesizer
voltage-controlledoscillator (VCO)
摘要: Driven by the demand for lower cost, lower power, wider bandwidth and higher datarates in both wireless and wired communication systems, integrated circuits and systems areconstantly pushed toward higher operating frequencies and higher level of integration.Furthermore, due to the continuous devices scaling and the need to reduce the powerconsumption of the digital circuitry, it is therefore highly desirable to implement aphase-locked loop (PLL) that can operate at a high frequency beyond ten GHz. In this project,we plan to design a 20-GHz low-noise fully-integrated frequency synthesizer based on PLLfor high-frequency wide-bandwidth applications. The high frequency building blocks of thePLL, i.e., the prescaler and the voltage-controlled oscillator (VCO) are particularly discussed,respectively. In the design of the prescaler, a high-speed logic flip-flops and D flip-flops isintroduced and analyzed. The circuits achieve high-speed by sharing the delay between thecombination logic blocks and the storge elements. By the way, it is suitable for realizinghigh-speed synchronous counters. For the VCO an oscillator based on the resonance of anLC-tank is the only one that gives a sufficiently high output frequency with a low noise. Thefully integrated VCO with spiral inductors has been implemented in standard CMOSprocesses. The VCO is proposed by using a new tunable inductance without a traditionalvaractor. This way can increase both operating frequency and tuning range. Bothhigh-frequency building blocks are combined together with the low-frequency parts of a PLL,such as the phase detector, the charge pump, and the second-order low-pass filter, in athird-order charge pump PLL frequency synthesizer that aims at the high-performancecommunications. With the multi-modulus prescaler, the PLL is able to generate an oscillationfrequency which is an integral multiple of the reference frequency. The PLL will be realizedin a standard 0.13-m or 0.09-m CMOS technology with a 1-V power supply, and the powerconsumption is smaller than 30mW and the phase noise is below -110 dBc/Hz at 1-MHzoffset. In response to these designs, there is a continued search for architectures and circuittechniques enabling a monolithic solution to meet our specifications with reasonable chip areaand power dissipation.
隨著低成本、低功率、寬頻和高資料率的無線和有線通信系統需求之趨勢,積體電路系統不斷地往較高工作頻率和高度積體化的技術發展。此外,由於元件縮小化的持續進行和數位電路降低功率的需要,使得需要實現一個超過十GHz 鎖相迴路以符合未來應用於寬頻和高資料率的應用。此計畫中,我們欲實現一個20GHz 的全積體化低雜訊鎖相迴路頻率合成器之設計。其中,此鎖相迴路的高頻電路有二塊:前置分頻器和電壓控制振盪器。對於前置分頻器之設計,我們採用高速邏輯正反器和D 型正反器,並予以說明和分析。它是利用消削組合邏輯和記憶元件的延遲效應的技術,而達到高速的目的;這樣一來,此電路就非常適合設計於高速的同步計數器。對於電壓控制振盪器之設計,是以電感—電容共振為架構,它是唯一具有高頻率且低雜訊的線路。這種以標準金氧半製程設計了高頻電壓控制振盪器,它是採用螺線型電感設計。電壓控制振盪器採用新型可調整式電感技術來設計,無需傳統方式的可變電容,這樣可以提升工作頻率和可調頻率範圍。有了以上兩個高頻電路,再結合鎖相迴路的低頻元件,如相位比較器、充電泵以及二階低通濾波器,設計出一個三階的充電泵鎖相迴路頻率合成器,目標是要達到通信上的要求。由於是採用多模的前置分頻器,此鎖相迴路可產生參考頻率的整數倍率之輸出頻率。我們將以0.13-微米或0.09-微米金氧半技術設計此電路,工作電壓為1 伏特,消耗功率需小於30 毫瓦,相位雜訊在1 MHz 偏移處為小於110 dBc/Hz。對應到這些設計,仍存在著很多的架構和電路技術用來實現單晶片的解決之道,同時也具備著合理的晶片面積和消耗功率以符合我們的規格之需求。
其他識別: NSC97-2221-E005-090
Appears in Collections:電機工程學系所



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