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標題: High Throughput Channel Decoding Chip Design for OFDM Based Optical Fiber Communications
作者: 林泓均
關鍵字: optical fiber communication
電子電機工程類, 電信工程
Shannon limit
net coding gain
摘要: It is well known that huge amount of information can be transmitted by optical fiberswith extremely small signal degradation even for transmission of long distances. Usually, thesignal is attenuated by 1/10 for a 50km distance in fibers, so repeaters for amplification ofsignals and reduction of noise can be eliminated.Even though the quality of optical fiber transmission is excellent, many noise sourcesstill exist, for example, the processes of electric signals converted to light signals and lightsignals converted back to electric signals. Besides, the noise will be more serious for theorthogonal frequency demultiplexing/multiplexing (OFDM) systems in the 64QAM ofpassive optical network (PON) and the 16QAM of radio over fiber (ROF). The messages areeven transmitted wirelessly in a very short distance for the latter system, unlike conventionalfiber system transmitting 0 and 1 only. In order to overcome the performance limitation ofsignal to noise ratio (SNR), forward error correction (FEC) has been widely applied in longdistance optical communications. It can improve bit error rate (BER) for higher SNR. Thus,FEC plays an important role in communications.In conventional optical fiber communications, the FEC usually adopts theReed-Solomon (RS) decoding method, but it is more appropriate for burst error correction.However, in OFDM based optical communications, many researchers started to employ lowdensity parity check (LDPC) decoding technique, since it can theoretically approach thefamous Shannon limit. If the RS decoder is allied with the LDPC decoder, it has beenreported that the error floor happened in LDPC decoding can be improved. In thissub-project, these two decoding methods will be combined to achieve more than 10dB netcoding gain with throughput close to 10Gbps. The biggest challenge in design is highthroughput. Therefore, large number of parallel process units is required, but the chip areaand power consumption will be extremely large. Our goal is to design the cost-effectivedecoding chip with smaller area and power consumption without losing error correctioncapabilityAnother important issue of this sub-project is to closely cooperate with the OFDMbaseband design in Sub-project 1. We need to integrate system simulations, FPGAverifications, and testing for integrated chips. It is expected to develop high-speed signalprocessors for digital communications to complete the mission of the project.
眾所周知光纖通訊可以傳送大量資訊,即使傳送通過長距離,信號也不易衰減,通常進行五十公里才會衰減十分之一,所以可以減少許多為了增強及去除雜訊而設置的轉發器(repeater)。雖然光纖傳送訊號的品質相當好,但將電轉光、再由光轉電之各項環節,還是會產生各種雜訊,尤其本計劃之傳收方式是正交分頻多工(OFDM)系統,使用64 QAM 調變技術於Passive Optical Network (PON)與16 QAM 調變技術於Radio OverFiber (ROF),後者有部分媒介可能以無線方式傳送,不像一般光纖通訊只傳0 與1,因此雜訊的影響將更為嚴重,為了克服接收訊號訊雜比(SNR)對效能的限制,正向錯誤更正(FEC)已經在高速率長距離光纖通訊系統中廣泛使用,它改善了SNR 對位元錯誤率(BER)的限制,因此FEC 在通訊領域是相當重要的一環。在傳統之光纖通訊中,FEC 通常是以Reed-Solomon(RS)編解碼為主,但比較適合突發連續錯誤之糾錯,而在OFDM 處理之光纖通訊,已陸續有許多學者使用低密度奇偶查核(LDPC)解碼技術,因為它能接近媒介容量的審農(Shannon)極限,若配合RS 解碼,有文獻報告具有改善錯誤底限(error floor)發生機會,因此本子計畫將結合此二種解碼方法,希望能達淨編碼增益達10dB 以上,且傳輸率可接近10Gbps 之解碼晶片。設計上的最大挑戰是高產出(high throughput),必須有大量的平行處理單元,如此將造成晶片面積與功耗過大,因此如何在不損失糾錯效能,又能達高產出的要求下,盡量降低晶片面積與功耗,以達經濟而實用之解碼晶片,將是本子計畫的目標。本子計畫的另一重點是必須與子計畫一之OFDM 基頻密切合作,無論在系統模擬、快速雛型製作(FPGA)驗證、晶片整合測試都要整合執行,以期能設計一功能完整之高速數位通訊信號處理系統,達成總計劃的任務。
其他識別: NSC99-2221-E005-111
Appears in Collections:電機工程學系所



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