Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/49014
標題: High Throughput Channel Decoding Chip Design for Ofdm Based Optical Fiber Communication Systems
適用於下世代混合光纖通訊系統之正交分頻多工接收機晶片設計-子計畫五:應用於正交分頻多工混合光纖通訊系統之高吞吐量通道解碼晶片設計(I)
作者: 林泓均
關鍵字: 電子電機工程類
技術發展
optical fiber communication
OFDM
FEC
BER
LDPC
throughput
Shannon limit
error floor
net coding gain
摘要: It is well known that huge amount of information can be transmitted by optical fiberswith excellent transmission quality. However, many noise sources still exist, for example, theprocesses of electric signals converted to light signals and light signals converted back toelectric signals. Besides, the noise will be more serious for the orthogonal frequencydemultiplexing/multiplexing (OFDM) systems in the 64QAM of passive optical network(PON) and the 16QAM/QPSK of radio over fiber (ROF). The messages are even transmittedwirelessly in a very short distance for the latter system, unlike conventional fiber systemtransmitting 0 and 1 only. In order to overcome the performance limitation of signal to noiseratio (SNR), forward error correction (FEC) has been widely applied in long distance opticalfiber and wireless communication systems. It can improve bit error rate (BER) for higherSNR.In conventional optical fiber communications, the FEC usually adopts theReed-Solomon (RS) decoding method, but it is more appropriate for burst error correction.However, in OFDM based optical communications, many researchers started to employ lowdensity parity check (LDPC) decoding technique, since it can theoretically approach thefamous Shannon limit. Furthermore, it is suitable for parallel processing to achieve highthroughput. However, highly parallelized LDPC requires large chip area and high powerconsumption. Besides, error floors usually occur at small BER. In this sub-project, we willdevelop some special post processing technique to alleviate error floor problems and achievemore than 10dB net coding gain with throughput close to 10Gbps. The biggest challenge indesign is high throughput. Therefore, large number of parallel process units is required, butthe chip area and power consumption will be extremely large. Our goal is to design thecost-effective decoding chip with smaller area and power consumption without losing errorcorrection capabilityAnother important work of this sub-project is to closely cooperate with the OFDMbaseband design in Sub-project 1. We need to integrate system simulations, FPGAverifications, and measure chips for integration. It is expected to develop high-speed signalprocessors for digital communications to reach the mission of the project.
眾所周知光纖通訊可以傳送大量資訊,而且傳送訊號的品質相當好,但將電轉光、再由光轉電之各項環節,還是會產生各種雜訊,尤其本計劃之傳收方式是正交分頻多工(OFDM)系統,使用64 QAM調變技術於Passive Optical Network (PON)與16 QAM/QPSK調變技術於Radio Over Fiber (ROF),後者有部分媒介以無線方式傳送,不像一般光纖通訊只傳0 與1,因此雜訊的影響將更為嚴重,為了克服接收訊號訊雜比(SNR)對效能的限制,正向錯誤更正(FEC)已經在高速率長距離光纖通訊系統與無線通訊系統中廣泛使用,它改善了SNR 對位元錯誤率(BER)的限制。在傳統之光纖通訊中,FEC 通常是以Reed-Solomon(RS)編解碼為主,但比較適合突發連續錯誤之糾錯,而在OFDM 處理之光纖通訊,已陸續有許多學者使用低密度奇偶查核(LDPC)解碼技術,因為它能接近媒介容量的審農(Shannon)極限,而且高度平行化,所以適合高吞吐量的應用,不過實務上,高度平行化的LDPC 需要占用大的晶片面積與高功耗,此外,當BER 極小時容易產生錯誤底限(error floor),因此本子計畫將運用特殊之後處理器來改善錯誤底限的問題,希望能達淨編碼增益達10dB 以上,且傳輸率可接近10Gbps 之解碼晶片。設計上的最大挑戰是高吞吐量(high throughput),必須有大量的平行處理單元,如此將造成晶片面積與功耗過大,因此如何在不損失糾錯效能,又能達高產出的要求下,盡量降低晶片面積與功耗,以達經濟而實用之解碼晶片,將是本子計畫的目標。本子計畫的另一重點是必須與子計畫一之OFDM 基頻密切合作,無論在系統模擬、快速雛型製作(FPGA) 整合驗證、晶片設計與測試都要有整合的考量,以期能設計一功能完整之高速數位通訊信號處理系統,達成總計劃的任務。
URI: http://hdl.handle.net/11455/49014
其他識別: NSC100-2221-E005-042
Appears in Collections:電機工程學系所

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