Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/5986
標題: IEEE 802.11b無線區域網路系統之決策迴授等化器設計
Design of a Decision Feedback Equalizer for IEEE 802.11b WLAN System
作者: 林心蕾
Lin, Hsin-Lei
關鍵字: decision feedbaack equalizer
決策迴授等化器
出版社: 電機工程學系
摘要: 本篇論文中,將介紹一個以IEEE 802.11b協定為基礎之決策迴授等化器設計。此等化器之濾波器部分,以雙重6個分接頭(dual 6-tap)的前置濾波器及雙重8個分接頭(dual 8-tap)迴授濾波器組成,輸入資料之位元數分別為6位元及2位元,而其架構乃由有限個數之脈衝響應濾波器(FIR)實現。等化器的輸出信號則是依據後端互補碼調變(CCK)之需求,而利用決策器將訊號切成兩個層次。最小均方(LMS)演算法估測通道,以對此平行架構之決策迴授等化器在其係數做更新。在TSMC 0.35 m CMOS 1p4m技術下,所模擬的最長路徑消耗時間為19.46 nsec。總面積為58624個閘數目。操作在3.3V的供應電壓下之功率消耗為25.087 mW。
In this thesis, design of a decision feedback equalizer (DFE) based on IEEE 802.11b protocol is presented. It has dual 6-tap feed-forward filters with 6-bit input and an 8-tap feedback filter with 2-bit input, that all the filters are implemented using the finite impulse response (FIR) filter. The output of the DFE is sliced into two levels by detector for CCK (8-chip complementary code keying) modulation. The least mean square (LMS) algorithm is used for updating the coefficients in the parallel DFE architecture. The data elapse time in the critical path is 19.46 nsec. The DFE is implemented using the TSMC 0.35 m CMOS 1p4m technology. The total gate count is 58624. The power consumption is 25.087 mW operating under a 3.3 V supply voltage.
URI: http://hdl.handle.net/11455/5986
Appears in Collections:電機工程學系所

文件中的檔案:

取得全文請前往華藝線上圖書館



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.