Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6267
標題: 應用於無線區域網路802.11a/b/g與60GHz之低雜訊放大器設計
The Low Noise Amplifier Design for WLAN 802.11a/b/g and 60GHz Applications
作者: 張綺真
Chang, Chi-Chen
關鍵字: dual-band
雙頻帶
GaAs
LNA
90nm CMOS
noise figure
60GHz
V-band
WLAN 802.11a/b/g
砷化鎵
低雜訊放大器
90奈米CMOS
雜訊指數
60GHz
V頻帶
無線區域網路802.11a/b/g
出版社: 電機工程學系所
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摘要: 本論文主要探討射頻接收器之低雜訊放大器設計,應用頻帶有802.11 a/b/g雙頻帶以及60GHz等,其中包含頻帶及應用介紹、文獻回顧、電路設計、晶片量測結果與結果討論等。主要以四個章節論述低雜訊放大器設計基礎以及電路實現。 第一章介紹無線射頻系統、IEEE 802.11頻帶及光纖傳輸與無線通訊系統發展。第二章以低雜訊放大器重要參數做介紹,其中包含低雜訊放大器簡介、阻抗匹配原理、匹配網路設計、雜訊指數、線性度以及穩定度等介紹。 第三章為應用雙頻帶之1伏供應電壓CMOS低雜訊放大器設計,探討三種常見用於低雜訊放大器組態,包含匹配設計以及雜訊能力。利用摺疊疊接組態的低電壓特性,設計低功耗電路。晶片使用TSMC 0.18um CMOS製程,2.4GHz與5GHz量測增益值分別為13.9 dB以及9.6 dB,量測雜訊指數值為3.9 dB與4.7dB。電路操作於1V電壓下功耗為5.5 mW。 第四章為砷化鎵製程之60GHz低雜訊放大器設計,探討砷化鎵製程優異的特性以及應用範圍。以WIN 0.15um pHEMT 製程設計,量測增益於55.7 GHz為11 dB,雜訊指數為4.8 dB。電路操作於1.8 V電壓下功耗為26.6mW。第五章為90奈米製程之60GHz低雜訊放大器設計,使用TSMC 90nm CMOS製程。量測增益於59GHz為6.57dB,雜訊指數為7.4dB。電路操作於1.2V電壓下功耗為9.84mW。
This thesis focuses on the low noise amplifier design of RF receivers for WLAN 802.11a/b/g dual-band and 60GHz applications, in which we cover the topics including introduction to bands and applications, literature review, circuit designs, chips' measurement results and discussions of the results. There are four chapters to discourse on the basis of low noise amplifier design, and circuit implementations. In Chapter 1, we introduce the wireless RF system, IEEE 802.11 bands, and optical transmission and wireless communications systems development. In Chapter 2, important parameters of LNA are described, including introduction, impedance matching theory, matching network design, noise figure, linearity, and stability. Chapter 3 is focused on the design of a sub 1V CMOS low noise amplifier for dual-band application. This chapter starts from studying three basic topologies for LNA, including their matching design and noise ability. Then we use low voltage characteristics of the folded cascode circuit to design a low power consumption circuit for 2.4GHz/5GHz dual band application. The chip is implemented using TSMC 0.18um CMOS process technology. The measured peak gains are 13.9 dB and 9.6dB at frequencies 2.4GHz and 5GHz, respectively. The measured noise figures are 3.9 dB and 4.7 dB, respectively, for both bands. The power consumption of the circuit is 5.5mW under 1V supply voltage. The subject of Chapter 4 is the 60GHz low noise amplifier design using GaAs process technology, and probing the technology behavior of the GaAs process and its applications. This chip is fabricated using WIN 0.15um pHEMT process. The measured peak gain of this 60GHz GaAs LNA is 11dB at 55.7GHz, and the measured noise figure is 4.8dB. The power consumption of the circuit is 26.6mW under 1.8V supply voltage. In Chapter 5, a 60GHz LNA using TSMC 90nm CMOS process technology is presented. The measurement results show a 6.57 dB gain and a 7.4 dB noise figure at 59GHz. The power consumption of the circuit is 9.4mW under 1.2V supply voltage.
URI: http://hdl.handle.net/11455/6267
其他識別: U0005-0808201116041700
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