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The RF Receiver Front-End Circuit Design for WLAN 802.11a, 24GHz and 60GHz Applications
|關鍵字:||current bleeding technique|
low noise technique
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This thesis presents the receiver RFIC design for three band applications: WLAN 802.11a, 24GHz, and 60GHz, including circuit design and system conception. It is composed of four main parts: mixer design theorem, mixer design for WLAN 802.11a application, mixer and the receiver front end design for 24GHz application, and mixer design for 60GHz application. In each part, the content includes the circuit design, system analysis, chip measurement results, and a short discussion. In chapter two, we introduce design theorem for mixers, and we discuss general considerations in the design of mixers. Furthermore, we describe conventional mixer topologies and performance parameters for mixers. In chapter three, an ultra low noise mixer design by using current bleeding and switching bias technique for WLAN 802.11a application is presented. The circuit is implemented in the TSMC 0.18μm CMOS process technology. We operate the direct down conversion mixer for the RF being 5.2GHz and the IF being 50MHz. The measured power conversion gain is 4.785dB, P1dB is -13dBm, and noise figure is 7.155dB. The power consumption of the proposed mixer is 9.72mW under 1.8V supply voltage. In chapter four, a mixer design and a receiver front end design for 24GHz applications are presented. Both designs are implemented in TSMC 0.18μm CMOS process technology. The first mixer directly down-converts the RF signal from 24GHz to IF 50MHz band using the improved current bleeding technology. The measurement results: show that the power conversion gain is 8.2dB, P1dB is -8.4dBm, and the noise figure is 11.6dB. The proposed mixer consumes 5.544mW dc power from the 1.8-V supply. The measured data show good balance between linearity and power conversion gain. The second circuit in this chapter is composed of a low noise amplifier and a mixer for 24GHz applications, in which the LNA uses resistive feedback and linearity improvement technology and the first circuit in this chapter is adopted as well. The simulation results show that the power conversion gain is 23.674dB, P1dB is -23.9dBm, and the noise figure is 5.2dB. The power consumption of the proposed receiver front end is 33.948mW under a 1.8V supply voltage. In chapter five, the mixer design for 60GHz application which is implemented in TSMC 90nm CMOS process technology is presented. The proposed mixer down-converts the RF signal from 60GHz to 12GHz IF band using the square-law topology. The measurement results show that the power conversion gain is 4.567dB, P1dB is-4dBm, and the noise figure is 14.925dB. The power consumption of the proposed mixer is 3.7mW under 1.2V supply.
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