Please use this identifier to cite or link to this item:
Design and Analysis of High Speed Frequency Synthesizers Using an Integrated Transformer-Based Feedback Technique
|引用:|| B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2000.  B. Razavi, “Design of integrated circuits for optical communications,” McGraw-Hill, 2003.  N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuits, vol. 27, pp. 810-820, May 1992.  D. M. Pozar, “Microwave Engineering Third Edition,” Wiley, 2005.  M. Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1018-1024, July 2001.  J. Maget, M. Tiebout, and R. Kraus, “MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1139-1147, July 2003.  R. Castello, P. Erratico, S. Manizini, and F. Svelto, “ A 30% tuning range varactor compatible with future scaled technologies,” in Proc. Symp. VLSI Circuits, pp. 34-35, 1998.  F. Svelto, S. Manizini and R. Castello, “ A three terminal varactor for RFICs in standard CMOS technology,” IEEE Trans. Electron Devices, vol.47, pp. 893-895, Apr. 2000.  J. Maget, M. Tiebout, and R. Kraus, “ Influence of novel MOS varactors on the performance of a fully integrated UMTS VCO in standard 0.25-um CMOS technology, “ IEEE J. Solid-State Circuits, vol. 37, pp. 953-958 , July 2002.  B. Razavi, “RF Microelectronics,” Prentice Hall, Upper Saddle River, NJ 07458.  N. M. Nguyen and R. G. Meyer, “Si IC-compatible inductors and LC passive filters,” IEEE J. Solid-State Circuits, vol. 25, pp. 1028-1031, Aug. 1990.  R. B. Merrill, T.W. Lee, Y. Hong, R. Rasmussen, L.A. Moberly, , “Optimization of high Q inductors for multi-level metal CMOS,“ in Proc. International Electron Devices Meeting (IEDM), pp. 983-986, Dec. 1995.  Y. Park, S. Chakraborty, C. H. Lee, S. Nuttinck and J. Laskar., “Wide-band CMOS VCO and frequency divider design for quadrature signal generation,” IEEE Microwave Symp. Dig., vol. 3, pp. 1493 - 1496, 2004.  Z. Wang, H. S. Savci, N. S. Dogan, “1-V ultra-low-power CMOS LC VCO for UHF quadrature signal generation,” in Proc. IEEE International Symposium on Circuits and System (ISCAS), pp. 4022-4025, 2006.  A. Hajimiri, T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. of Solid-State Circuits, vol. 34, pp. 717-724, May 1999.  T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,“ IEEE J. Solid-State Circuits, vol. 35, pp. 326-336, Mar. 2000.  J. J. Kim and B. Kim, “A low phase noise CMOS LC oscillator with a ring structure,” in Int. Solid-State Circuits (ISSCC) Dig. Tech. Papers, pp. 430-475, Feb. 2000.  T. P. Liu, “A 6.5GHz monolithic CMOS voltage-controlled oscillator,” in Int. Solid-State Circuits (ISSCC) Dig. Tech. Papers, pp. 405-405, Feb. 1999.  C. Lam and B. Razavi, “A 2.6-GHz/5.2-GHz CMOS voltage-controlled oscillator,” in Int. Solid-State Circuits (ISSCC) Dig. Tech. Papers, pp. 402-403, Feb. 1999.  J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with frequency detection,” in Int. Solid-State Circuits (ISSCC) Dig. Tech. Papers, pp. 78-79, Feb. 2001.  J. van der Tang, P. van de Ven, D. Kasperkovitz, A. van Roermund, “Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator,” IEEE J. Solid-State Circuits, vol. 37, pp. 657-661, MAY 2002.  T. Teung, Analysis and Design of On-chip Spiral Inductors and Transformers for Silicon RF Integrated Circuits, Master thesis, Hong Kong University of Science and Technology, 1998.  J. Kim, M. A. Horowitz, G.Y. Wei, “Design of CMOS Adaptive-Bandwidth PLL/DLLs: A General Approach,” IEEE Transaction on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, no.11, pp.860-869, Nov.2003.  J. J Rael and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” in Proc. IEEE Custom Integrated Circuit Conf. (CICC), Sep. 2000, pp. 569-572.  E. Hegazi, J. Rael, A. A. Abidi, The Designer's Guide to High-Purity Oscillators, Kluwer Acdemic Publishers, 2005.  K. Andreani and H. Sjoland, “Tail current noise suppression in RF CMOS VCOs,” IEEE J.Solid-State Circuits, vol. 37, no. 3, pp. 342-348, Mar. 2002.  B. Muer, M. Borremans, M. Steyaert and G. Puma, “A 2-GHz low-phase-noise integratedLC-VCO set with flicker-noise upconversion minimization,” IEEE J. Solid-State Circuits, vol.35, no. 7, pp. 1034-11038, Jul. 2000.  T. Soorapanth and S. S. Wong, “A 0-dB IL 2140±30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 579-586, May 2002.  A. Worapishet, “Extended phase noise performance in mutual negative resistance CMOS LC oscillator for low supply voltages,” IEICE Trans. Electron., vol. e89-c, no. 6, pp. 732-738, Jun.2006.  D. B. Leeson, “A simple model of feedback oscillator noise spectrum,'' Proc. IEEE, vol. 54, no. 2, pp. 329-330, Feb. 1966.  J. Kim, M. A. Horowitz, G.Y. Wei, “Design of CMOS Adaptive-Bandwidth PLL/DLLs: A General Approach,” IEEE Transaction on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, no.11, pp.860-869, Nov.2003.  B. Bornoosh, A. Afzali-Kusha, R. Dehghani, M. Mehrara, S.M. Atarodi and M. Nourani, “Reduced complexity 1-bit higher-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis application,” IEEE Proc. Circuits Devices System, vol. 152, no. 5, October 2005.  J. J Zhou and D. J. Allstot, “Monolithic transformers and their application in a differential CMOS RF low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2020-2027, Dec. 1998.  B. A. Floyd, “Sub-integer frequency synthesis using phase-rotating frequency dividers,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 55, no. 7, pp. 1823-1833, Aug. 2008.  H.-H. Hsieh, Y.-C. Hsu, and L.-H. Lu, “A 15/30-GHz dual-band multiphase voltage-controlled oscillator in 0.18-μm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 3, pp. 474-483, Mar. 2007.  P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1737-1747, Dec. 2002.  S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, and V. Boccuzzi, “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1148-1154, July 2003.  A. P. van der Wel, E. A. M. Klumperink, and B. Nauta, “Measurement of MOSFET LF noise under large signal RF excitation,” in Proc. Eur. Solid-State Device Research Conf., Sept. 2002, pp. 91-94.  J. Craninckx and M. Steyaert, “A 1.75-GHz/3-V dual-modulus divideby-128/129 prescaler in 0.7-μm CMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 890-897, July 1996.  H.-K. Chen, H.-J. Chen, D.-C. Chang, Y.-Z. Juang, and S.-S. Lu, “A 0.6 V, 4.32 mW, 68 GHz low phase-noise VCO with intrinsic-tuned technique in 0.13um CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 7, pp. 467-469, July 2008.  S.-L. Jang. C.-J. Huang, C.-W. Hsue, and C.-W. Chang, “A 0.3 V cross-coupled VCO using dynamic threshold MOSFET,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 3, pp. 166-168, Mar. 2010.  T. Soorapanth and S.S Wong, “A 0-dB IL 2410 30MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS,” IEEE J. Solid-State Circuits, vol.37, no.5 pp.579-586, May 2002.  P. Andreani and S.Mattisson, “On the Use of MOS Varactors in RF VCO's,” IEEE J. Solid-State Circuits, vol.35, no.6 pp.905-910, June 2000.  F. Piazza and Q. Huang, “A low power CMOS dual modulus prescaler for high-speed frequency synthesizer,” IEICE Trans. Electron., vol.E80-C, no.2, pp.314-319, Feb. 1997.  J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol.24, no.1, pp.62-70, Feb. 1989.  H.R. Rategh, et al., “Superharmonic injection locked oscillators as low power frequency dividers,” Symp. VLSI Circuits, pp. 132-135, Jun. 1998.  M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” J. Solid-State Circuits, pp. 1170-1174, vol. 39 no. 7, July 2004.  A. Mazzanti, et al., “Analysis and design of injection-lock LC dividers for quadrature generation,” J. Solid-State Circuits, pp. 1425-1433, vol. 39, no. 9, Sep. 2004.  S. Yu and P. Kinget, “A 0.65V 2.5GHz fractional-N frequency synthesizer in 90nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 304-305.  S. Pellerano, et al., “A 39.1-to-41.6 GHz ΔΣ fractional-N frequency synthesizer in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 484-485, Feb. 2008.  O. Richard, et al., “A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications,” ISSCC Dig. Tech. Papers, pp. 252-253, Feb. 2010.  Z. Li and K. K. O, “A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1296-1302, Jun. 2005.  K. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 652-660, Mar. 2005.  H.-H. Hsieh, Y.-C. Hsu, and L.-H. Lu, “A 15/30-GHz dual-band multiphase voltage-controlled oscillator in 0.18-μm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 3, pp. 474-483, Mar. 2007.|
This thesis describes the feasibility study of variable inductance realized with integrated transformer and frequency synthesis based on phase-locked loop technique. There are five major parts in this thesis discussed in detail. The first part of this thesis discusses the traditional LC VCO applied capacitive varactors and its disadvantages. The proposed structures employ integrated transformers as inductance with voltage-controlled value. The traditional approach of tuning the VCO oscillation frequency by capacitance variation would be sacrificed, while the proposed structure with induction variation will be applied to substitute for that. Two kinds of the VCOs are proposed. One is the gain-controlled oscillator, and the other is the transconductance-controlled oscillator. The second part of the thesis would introduce the concept of phase-locked loop, and describe about how it operates. The differences between integer-N and fractional-N frequency synthesizer, in addition to the fractional-N one realized with a delta-sigma modulator would be discussed. The third part is designing a low supply voltage circuit without decreasing the Vt of the MOS transistor, while the oscillated signals of the tank translate through the ground node or the supply voltage node. By this way, these signals through the ground node and the supply voltage node oscillate at the same time and might operate at a low voltage supply and also decrease the supply noise. The fourth part introduces several techniques to promote operation frequency and the tuning frequency range. In the last part, we use a current reused technique to reduce the circuit power consumption. The high-frequency and low-voltage design employs the technique and concept of current reuse to achieve the high frequency and low power phase-locked loop design.
|Appears in Collections:||電機工程學系所|
Show full item record
TAIR Related Article
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.