Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6543
標題: 低功率嵌入式非揮發性記憶體系統及控制信號產生電路設計
Design of Low-Power Embedded Nonvolatile Memory System and Control Signal Generator
作者: 陳志興
Chen, Zhi-Xing
關鍵字: Embedded
嵌入式
Nonvolatile
Memory
Control
Signal
非揮發性
記憶體
控制
信號
出版社: 電機工程學系所
引用: [1] B. Razavi,李峻霣譯, ”類比CMOS積體電路設計,”滄海書局,中華民國九十三年一月. [2] N. H. E. Weste, K. Eshraghian,黃淑娟譯, ”CMOS VLSI設計原理,” 偉明圖書有限公司,中華民國九十一年十一月. [3] 沈祐民, ” Multilevel Sensing ang Verifying Circuit for Flash Memory,” 2004年碩士論文,中興大學. [4] K. Itoh, ”VLSI Memory chip Design,”Springer,Jan., 2001 [5] G. Campardo, R. Micheloni, D. Novosel, ”VLSI-Design of Non-Volatile Memories,”Springer,Oct., 2004. [6] M. M. Mano, ” Digital Design,” Prentice Hall, Aug., 2001. [7] H.-F. A. Chou, et al., “Comprehensive study on a novel bi-directional tunneling program/erase NOR-type (Bi-NOR) 3-D flash memory cell,” IEEE Trans. Electron Devices, vol. 48, pp. 1386-1393, 2001. [8] C. –S. E. Yang, et al., “New buried bit-line NAND (Bi-NAND) Flash memory for data storage,” Symp. VLSI Tech. Dig., pp. 95-96, 2003. [9] A. Chrisanthopoulos, Y. Moisiadis, A. Varagis, Y. Tsiatouhas, and A. Arapoyanni, “A new Flash memory sense amplifier in 0.18 μm CMOS technology,” Proc. IEEE Int. Conf. Electronics, circuits, and Systems (ICECS), vol. 2, pp. 941-944, Sep., 2001. [10] J. F. Dickson, “On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol. sc-11, pp. 374-378, Jun., 1976. [11] Hong-chin Lin and Nai-Hsien Chen, “An Efficient Clock Scheme for Low-voltage Four-phase Charge Pumps,” IEEE Int. Symp. Circuits and Systems, vol. 1, pp. 504-507, 2001. [12] D. Hilbiber “A new Semiconductor voltage standard,” in ISSCC Dig. Tech. Papers, pp. 32-33, Feb. 1964. [13] K. E. Kujik. “A Precision Reference Voltage Source” IEEE J. Solid-State Circuits, vol. 8, pp. 222-226, Jun., 1973. [14] Kung-Hong Lee and Ya-Chin King, “New single-poly EEPROM with cell size down to 8F/sup 2/ for high density embedded nonvolatile memory applications,” VLSI Technology Symposium, Kyoto, Japan, pp. 93-94, 2003. [15] Kung-Hong Lee, Shih-Chen Wang, Ya-Chin King, “Self-convergent scheme for logic-process-based multilevel/analog memory,” Electron Devices, IEEE Transactions, pp. 2676 – 2681, Dec. 2005. [16] Kung-Hong Lee, Shih-Chen Wang, Ya-Chin King, “Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory,” Memory Technology , IEEE International Workshop , pp. 3-8, Aug. 2005. [17] R. Micheloni, L. Crippa, M. Sangalli, and G. Campardo, “The Flash Memory Read Path: Build Blocks and Critical Aspects,” proceedings of IEEE, pp. 537-553, Apr., 2003. [18] Chiu-Chiao Chung, Hong-chin Lin,Yen-Tai Lin, “A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories,” IEEE J. solid-state circuits, vol. 2,Feb., 2005. [19] Chiu-Chiao Chung, Hong-chin Lin,You-Min Shen and Yen-Tai Lin, “A Multilevel Sensing and Program verifying scheme for Bi-NAND Flash Memories,” IEEE VLSI-TSA International Symposium, pp. 267-270, apr., 2005. [20] 李昆鴻,”Study of High-Qensity Embedded Single-Polysilicon Nonvolatile Memory ,” 2005年博士論文,清華大學.
摘要: 在一般SOC的應用中,記憶體一直都是不可或缺的區塊之ㄧ,因此研究如何有效縮小記憶體面積、降低功率及減低成本將會是相當有意義的。最近有人提出一種利用標準0.35μm CMOS製程的Single-poly EEPROM記憶體結構,可達高密度、低成本以便應用於系統晶片(SOC)之嵌入式非揮發性記憶體。 本篇論文以此EEPROM作為記憶體系統的記憶元為基礎,並以對此記憶元作寫入及讀出為目標,設計所需的周邊電路,包括考慮寫入及讀出時可供給記憶元足夠驅動能力的驅動電壓的電壓驅動電路、考慮以交錯耦合電路架構來降低製程誤差的感測電路及精簡化以減少電路的複雜度的驗證電路,最後再設計一組控制信號產生器,用來產生在寫入及讀出時所需的控制信號,以便未來實現一套完整的嵌入式記憶體的矽智產。
In SOC applications, memory is always one of the necessary blocks, Therefore, it is important to investigate how to effectively minimize memory size, reduce power, and lower cost. Recently it has been proposed that a single-poly EEPROM memory structure using the standard 0.35μm CMOS process, achieves high density, low cost, to be applied to SOC as an embedded nonvolatile memory. This thesis is based on this kind of EEPROM as the memory cell to design the required peripheral circuits which are used to program and read the memory cell, including voltage drivers having enough drive ability for memory cells in program and read cycles, the sense amplifiers with cross-couple structures to reduce process mismatch and the simple verifying circuits to reduce complexity, finally, those circuits were combined with a control signal generator generating control signals for program and read, it well be applied to the complete silicon intellectual property (SIP) of the embedded nonvolatile memory in the future.
URI: http://hdl.handle.net/11455/6543
其他識別: U0005-2007200617002800
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2007200617002800
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