Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6624
標題: 應用於多輸入多輸出/正交分頻多工系統之高產量管線式快速傅利葉轉換硬體架構
A High Throughput Pipelined Fast Fourier Transform Architecture for MIMO-OFDM Systems
作者: 廖哲佑
Liao, Che-Yu
關鍵字: 快速傅利葉
FFT
正交分頻多工
多輸入多輸出
OFDM
MIMO
802.11
出版社: 電機工程學系所
引用: [1] IEEE 802.11a standard, Jun, 1999. [2] IEEE 802.11g standard, Jan, 2002. [3] IEEE 802.11b standard, Sep, 1999. [4] 林泓均、陳囿全、林心蕾、張振豪,“可處理雙輸入信號的管線式傅利葉轉換系統”,中華民國發明專利,第I254215號。 [5]樊國楨,林樹國, “無線網路的種類與相關標準淺談”, http://www.fisc.com.tw/FISCWeb/FISCBimonthly/Article.aspx?Volume=44&TNo=54 [6]禹帆, “無線通訊網路概論” 2002/05/31. [7]郭長祐, “Wi-Fi最為難的第三步:IEEE 802.11n Pre-n是加溫?先行? 超規?專屬?” http://tech.digitimes.com.tw/ShowNews.aspx?zCatId=134&zNotesDocId=01B0BF9D0667 054648256FD60044A758 , 2005/04/04. [8]陳囿全, “A Double-Rate Pipelined Fast Fourier Transform Architecture for OFDM Systems, ” 2004年碩士論文,中興大學. [9]鄭榮錄, “Comparison and FPGA Implementation of Single/Double Rate Pipelined FFT/IFFT Architecture , ” 2005年碩士論文,中興大學. [10]陳聖偉, “An Efficient High Speed Double-Rate Pipelined FFT/IFFT Architecture”, 2005年碩士論文,中興大學. [11]沈嘉, “OFDM:下一代無線通信技術風向標”, http://big5.ciweekly.com/gate/big5/www.enet.com.cn/article/2005/1021/A2 0051021464562.shtml ,2005/10/21. [12]洪嘉鴻, “MIMO強化WLAN涵蓋範圍與傳輸速率”, http://www.hope.com.tw/art/print.asp?O=200505051431097841 , 2005 [13] S. He. and M. Torkelson. “Design and Implementation of a 1024-point Pipeline FFT Processor.” in Proc. IEEE Custom Integrated Circuits Conference, pp.131-134, 1998. [14]江建銘, “管道式快速傅立葉轉換器之FPGA有效率實現設計”, 2004年碩士論文, 大同大學. [15] Yu-Wei Lin, Hsuan-Yu Liu, and Chen-Yi Lee, ”A 1 GS/s FFT/IFFT Processor for UWB Applications,” IEEE Journal of Solid-State Circuits, vol 40, pp. 1726 - 1735, Aug. 2005. [16] 林永藤, “適用於正交分頻多工系統的可變長度快速傅利葉轉換處理 器之設計與實作”,2000年碩士論文,台灣大學. [17] Hsuan-Yu Liu, Chien-Ching Lin, Yu-Wei Lin, Ching-Che Chung, Kai-Li Lin, Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, Chen-Yi Lee, “A 480Mb/s LDPC-COFDM-based UWB baseband transceiver”, IEEE Conference Proceeding, 6-10 Feb. 2005 Page(s). [18] Min-An Song, Lan-Da Van, Ting-Chun Huang, Sy-Yen Kuo, “A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers”, IEEE Conference Proceeding, Volume 1, 25-28 July 2004. [19] Shousheng HE, and Mats Torkelson, “Designing pipeline FFT processor for OFDM (de)modulation,” Signals, Systems, and Electronics, 1998, pp: 257 – 262, Oct. 1998 [20] Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu, “Implementation of a Programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems, ” IEEE Int. Sym. Circuit and Systems, vol. 2, pp. 121 - 124, May. 2003. [21] Shousheng HE, and Mats Torkelson, “Designing pipeline FFT processor for OFDM (de)modulation,” Signals, Systems, and Electronics, 1998, pp: 257 – 262, Oct. 1998 [22] Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu, “Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems, ” IEEE Int. Sym. Circuit and Systems, vol. 2, pp. 121 - 124, May. 2003 [23] Hsin-Lei Lin, Hongchin Lin, R. C. Chang, S.-W. Chen, C.-Y. Liao, C.-H. Wu, “A High-Speed Highly Pipelined 2n-Point FFT Architecture for A Dual OFDM Processor,” Intl. Conf. Mixed Design of Integrated Circuits and Systems, June. 22-24, 2006 [24] H.-L. Lin, H. Lin, Y.-C. Chen and R. C. Chang, "A Novel Pipelined Fast Fourier Transform Architecture for Double Rate OFDM Systems", Proceedings of IEEE Workshop on Signal Processing Systems, Oct. 2004, pp. 7-11 [25] C. Chiu, Wing Hui, Tiong Jiu Ding, J.V. McCanny, "A 64-point Fourier transform chip for video motion compensation using phase correlation", IEEE Journal of Solid-State Circuits, vol. 31, 1996, pp. 1751-1761 [26] T. Chen, G. Sunanda, and J. Jin, "COBRA: a 100-MOPS single-chip programmable and expandable FFT", IEEE Transation on VLSI, vol. 7, 1999, pp. 174-182 [27] K. Maharatna, E. Grass, U. Jagdhold, " A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM", IEEE Journal of Solid-State Circuits, vol. 39, 2004, pp. 484 – 493 [28] Y.-W. Lin, H.-Y. Liu, C.-Y. Lee, “A 1-GS/s FFT/IFFT Proecssor for UWB Applications”, IEEE Journal of Solid-State Circuits, vol. 40, 2005, pp. 1726-1735
摘要: 近年來,行動通訊科技隨著VLSI技術而快速發展,使得數位通訊系統的複雜設計變成可行,目前無線區域網路主流802.11a/b/g最高可提供54Mbps的傳輸速率已經不敷使用,因此IEEE開始制定802.11n。 雖然在IEEE 802.11n的制定上意見分岐,但是為了實現增加傳輸率所運用的技術有2個共通點,就是OFDM(Orthogonal Frequency Division Multiplexing)調變/解調技術,及MIMO(Multiple Input Multiple Output)發送/接收技術,本論文探討將來在MIMO-OFDM的系統中,FFT電路必會面臨面積過大,資料處理速度不夠快,電路功率消耗過大的問題,所以我們從Radix-2的FFT演算法中找到電路空閒的時間,並盡量利用運算過程中閒置的硬體以達高產量(High-Throughput)的目標,因為電路的共用使每一個Block使用率均達到100%,所以電路面積不會增加太多,此外,再利用硬體架構的改善增加硬體的效能,包括暫存器與Pipeline乘法器之改良架構。 本硬體設計經改善後採用TSMC 0.18µm 1P6M CMOS 製程,雙輸入資料的寬度設為10位元,電路於200MHz的執行速度下功率消耗70.39mW,晶片面積1.44mm2。
In the last few years, the development of mobile communication science and technology was extremely fast due to VLSI technology. Mary complicated design of digital communication system become feasible. Currently, the dominant WLAN products 802.11 a/b/g with 54Mbps transmission rate are not satisfied by the users. Thus IEEE is working on the new standard:802.11n. Although the constitution of 802.11n has not been unified yet, there are two algorithms to enhance the transmission rate. One is OFDM (Orthogonal Frequency Division Multiplexing)technology. Another one is MIMO (Multiple Input Multiple Output)technology. For the future MIMO-OFDM system, it is expected investigates that the FFT processor will have problems on large chip area,large power consumption and large computation time. Since the circuit of Radix-2 FFT contains a lot of hardware idled during computation, it should be efficient to make use of it as much as possible to increase the throughput. Due to hardware sharing,the chip area increment is quite small,while almost all the functional bock have no time to be idled. To enhance the hardware performance, the hardware archichecture was also improved, for example pipelined multipliers and registers. After the improvement, the core size of the proposed architecture is 1.44mm2 with the power consumption of 70.39mW at clock rate of 200MHz for dual paths of data inputs with 10-bit word length using TSMC 0.18µm 1P6M CMOS technology.
URI: http://hdl.handle.net/11455/6624
其他識別: U0005-2107200614071400
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2107200614071400
Appears in Collections:電機工程學系所

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