請用此 Handle URI 來引用此文件: http://hdl.handle.net/11455/6815
標題: 以類比式弦波轉換器實現直接數位頻率合成器
Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique
作者: 翁峻鴻
Weng, Jun-Hong
關鍵字: 直接數位頻率合成器
DDFS,
鎖相迴路
數位類比轉換器
PLL
DAC
出版社: 電機工程學系所
引用: [1] B.G. Goldberg, “Digital Techniques in Frequency Synthesis, McGraw-Hill, ”1999. [2] A. Gutierrez-Aitken, J. Matsui, E. N. Kaneshiro, B. K. Oyama, D. Sawdai, A. Oki, and D. C. Streit, “ Ultra high speed direct digital synthesizer using InP DHBT technology,” IEEE J. Solid-State Circuits, vol. 37, no. 9, pp. 1115-121,K.Sep. 2002 [3] S. E. Turner and D. E. Kotecki, “Direct digital synthesizer with ROMless architecture at 13-GHz clock frequency in InP DHBT technology,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 296-298, May 2006. [4] S. E. Turner and D. E. Kotecki, “Direct digital synthesizer with sine-weighted DAC at 32-GHz clock frequency in InP DHBT technology,” IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2284-2290, Oct. 2006. [5] K. R. Elliott, “Direct digital synthesis: for enabling next generation RF systems, ” in CSIC Dig.,Nov.2005, pp, 125-128. [6] X. Yu, F. F. Dai, J. D. Irwin, R. C. Jaeger, “A 12 GHz 1.9 W direct digital synthesizer MMIC implemented in 0.18-um SiGe BiCMOS Technology,” IEEE J. Solid-State Circuits, vol.43, no. 6, pp.1384-1393, June 2008. [7] X. Geng, F. F. Dai, J. D. Irwin, R. C. Jaeger, “24-bit 5.0 GHz direct digital synthesizer RFIC with direct digital modulation in 0.13 um SiGe BiCMOS technology,” IEEE J. Solid-State Circuits, vol.45, no. 5, pp.944-954, May 2010. [8] S. Thuries, E. Tournier, A. Cathelin, S. Godet, and J. Graffeuil, “A 6-GHz low-power BiCMOS SiGe:C 0.25 um direct digital synthesizer,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 1, pp. 46-48, Jan. 2008. [9] J. Tierney, C. M. Rader, and B. Gold, “A digital frequency synthesizer,” IEEE Trans. Audio Electroacoust., vol. AU-19, pp. 48-57, 1971. [10] A. Ashrafi and R. Adhami, “Theoretical upperbound of the spurious-free dynamic range in direct digital frequency synthesizers realized by polynomial interpolation methods,” IEEE Trans. Circuit Syst.-I: Regular Paper, vol. 54, no. 10, pp. 2252-2261, Oct. 2007. [11] J. M. P. Langlois and D. Al-Khalili, “Phase to sinusoid amplitude conversion techniques for direct frequency synthesis,” in IEE Proc. Circuits Devices Syst., Dec. 2004, pp. 519-528. [12] D. A. Sunderland, R. A. Strauch, S. S. Wharfield, H. T. Peterson, and C. R. Cole, “CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications,” IEEE J. Solid-State Circuits, vol. sc-19, no. 4, pp. 497-506, Aug. 1984. [13] H. T. Nicholas III, H. Samueli, and B. Kim, “The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects,” in Proc. 42nd Annu. Frequency Control Symp., 1988, pp. 257-263. [14] C. C. Wang, Y. L. Tseng, H. C. She, C. C. Li, and R. Hu, “A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigeometric quadruple angle formula,” IEEE Trans. Very Large Scale Integration Syst., vol. 12, no. 9, pp. 895-900, Sep. 2004. [15] D. De Caro, N. Petra, and A. G. M. Strollo, “Reducing lookup-table size in direct digital frequency synthesizers using optimized multipartite table method,” IEEE Trans. Circuits Syst. I, vol. 55, no. 7, pp. 2116-2127, Aug. 2008. [16] S. Mortezapour and E. K. F. Lee, “Design of low-power ROM-less Direct digital frequency synthesizer using nonlinear digital-to-analog converter,” IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1350-1359, Oct. 1999. [17] A. N. Mohieldin, A. A. Emira, and E. Sanchez-Sinencio, “A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1235-1243, Oct. 2002. [18] J. Jiang and E. K. F. Lee, “A low-power seqment nonlinear DAC-based direct digital frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1326-1330, Oct. 2002. [19] A. McEwan and S. Collins, “Direct digital-frequency synthesis by analog interpolation,” IEEE Trans. Circuit & Systems-II: Express Briefs, vol. 53, no. 11, pp.1294-1298, Nov. 2006. [20] C. Yang and A. J. Mason, “Fully integrated seven-order frequency-range quadrature sinusoid signal generator,” IEEE Trans. Instrumentation & Measurement, vol. 58, no. 10, pp. 3481-3489, Oct. 2009. [21] W. A. Evans, “Accurate sine-function synthesis,” Electronic Circuits and Systems, vol. 2, no. 3, pp. 75-78, May 1978. [22] Robert G. Meyer, Willy M.C. Sansen ,Sik Lui,and Stefan Peeters “The differential pair as a triangle-sine wave converter,” IEEE J. Solid-State Circuits, June 1976. [23] John W. Fattaruso, and Robert G. Meyer “Triangle-to-sine wave conversion with MOS technology,” IEEE J. Solid-State Circuits, sc-20, no. 2, April 1985. [24] Gilbert, B., “Translinear circuits: a proposed classification”, Electron. Lett., vol. 11, pp. 14-16, 1975. [25] John W. Fattaruso, and Robert G. Meyer “Triangle-to-sine wave conversion with MOS technology,” IEEE J. Solid-State Circuits, sc-20, NO. 2, April 1985. [26] P.C. Hills “MOS triangle-to-sine wave convertor based on subthreshold operation ,”Electronics Letters 8th ,vol.26, n0.23, Nov. 1990. [27] A. V. d. Bosch, et al., “A 10-bit 1-GSample/s nyquist current-steering CMOS D/A converter”, IEEE J. Solid-State Circuits, vol. 36, no.3, May 2001. [28] S. Mortezapour and E. Lee, “A low power quadrature direct digital frequency synthesizer using nonlinear resistor string DAC's,” in Proc. 24th Europ. Solid-state Circuit Conf, Sept.1998, pp. 348-351. [29] T. M. Y Nakamura, et al., “A 80-MHz 8-b CMOS D/A converter”, IEEE J. Solid-State Circuits, vol. 21, pp. 983-988, Dec. 1986. [30] J. Lindeberg, J. Vankka, J. Sommarek, and K. Halonen, “A 1.5V direct digital synthesizer with tunable delta-sigma modulator in 0.13 um CMOS” IEEE J. Solid-State Circuits, vol.40, no.9, Sep. 2005. [31] D. D. Caro and A. G. M. Strollo, “High-performance direct digital frequency synthesizers in 0.25 um CMOS using dual-slope approximation” IEEE J. Solid-State Circuits, vol.40, no.11, Nov. 2005. [32] F. Dai, W. Ni, S. Yin, and R. C. Jaeger, “A direct digital frequency synthesizer with fourth-order phase domain noise shaper and 12-bit current-steering DAC” IEEE J. Solid-State Circuits, vol.41, no.4, April 2006. [33] C.-C. Wang, J.-M. Huang, Y.-L. Tseng, W.-J. Lin, and R. Hu, “Phase-adjustable pipelining ROM-less direct digital frequency synthesizer with a 41.66MHz output frequency,” IEEE Trans. Circuits Syst. II, vol.53, no.10, Oct. 2006. [34] D. D. Caro, N. Petra, and A. G. M. Strollo, “A 380MHZ direct digital synthesizer/mixer with hybrid CORDIC architecture in 0.25 um CMOS” IEEE J. Solid-State Circuits, vol. 42, no.1, Jan. 2007. [35] A. G. M. Strollo, D. DeCaro, and N. Petra, “A 630MHz, 76mW direct digital frequency synthesizer using enhanced ROM compression technique” IEEE J. Solid-State Circuits, vol.42, no.2, Feb. 2007. [36] S. Thuries, E. Tournier, A. Cathelin, S. Godet, J. Graffeuil, “A 6-GHz low-power BiCMOS SiGe:C 0.25 um direct digital synthesizer,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 1, pp.46-48, Jan. 2008. [37] X. Yu, F. F. Dai, J. D. Irwin, R. C. Jaeger, “A 9-bit quadrature direct digital synthesizer implemented in 0.18-um SiGe BiCMOS Technology,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 5, pp.1257-1266, May 2008. [38] Z. Zhou and G. S. L. Rue, “A 12-bit nonlinear DAC for direct digital frequency synthesis,” IEEE Trans. Circuits Syst. I: Regular Papers, vol.55, no.9, pp. 2459-2468, Oct. 2008. [39] Xueyang Geng, Fa Foster Dai, J.David Irwin, and Richard C.Jaeger”A 11-Bit 8.6GHz Direct Digital Synthesizer MMIC with 10 Bit segmented Sin-Weighted DAC”, IEEE J. Solid-State Circuits, vol. 45, no. 2, Feb. 2010 [40] Xueyang Geng, ,Fa Foster Dai, J.David Irwin Richard C.”A 9-bit 2.9GHz direct digital synthesizer MMIC with direct digital frequency and phase modulations”, IMS 2009 [41] J. Jiang, E. Lee, “A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter,” in Pro. Custom Integrated Circuits Conf., pp.165-168, Sep. 2001. [42] B.-D. Yang, et. al, “An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/A converter,” IEEE J. Solid-State Circuits, vol. 39, no.5, pp. 761-774, May 2004. [43] H. C. Yeoh, et. al, “A 1.3GHz 350mW hybrid direct digital frequency synhesizer in 90 nm CMOS,” in Pro. Symp. VLSI Circuits, pp.122-123, June 2009. [44] X. Yu, F. F. Dai, J. D. Irwin, and R. C. Jaeger, “A 9-bit quadrature direct digital synthesizer implemented in 0.18-um SiGe BiCMOS Technology,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 5, pp. 1257-1266, May 2008 [45] Hong Chang Yeoh, Jae-Hun Jung, Yun-Hwan Jung,and Kwang-Hyun Baek ”A 1.3GHz 350mW hybrid direct digital frequency synthesizer in 90nm CMOS” , in Pro. Symp. VLSI Circuits, 2009 [46] Xueyang Geng, Fa Foster Dai, J. David Irwin and Richard C.Faeger”A 5GHz direct digiter Synthesizer MMIC with direct modulation and spur randomization”, in Pro. Symp. RFIC, 2009. [47] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.
摘要: 本論文介紹直接數位頻率合成器的原理及架構的區別,並提出改善傳統架構的無記憶體式直接數位頻率合成器的方法。我們使用三角轉弦波信號的類比電路的作法,採取無記憶體式直接數位頻率合成器的優點,捨棄了記憶體,並結合了傳統直接數位頻率合成器所採用的線性的數位類比轉換器。比起一般的無記憶體式直接數位頻率合成器,在面積與功率消耗的特性,此方式更具有其優勢,設計上也較採用非線性的數位類比轉換器容易。此外,我們所用的三角轉弦波信號的類比電路是本篇論文的研究重點之一,因為一切的起源都由三角轉弦波信號的類比電路開始,論文中也詳盡的去研究、分析三角轉弦波信號的類比電路,並朝向高速的設計方式來實現無記憶體式直接數位頻率合成器。 本篇論文將有五顆晶片實作驗證,第一顆晶片為translinear電路運用CMOS 0.18 um製程,電路面積為0.51×0.58mm2,功率消耗約為19mW。第二顆晶片也是translinear電路改變製程為SiGe 0.35 um製程,電路面積為0.66×0.62mm2,功率消耗約為37mW。第三顆晶片使用差動對當類比弦波轉換器實現直接數位頻率合成器,使用CMOS 0.18 um製程,工作頻率最高達2GHz,SFDR工作頻率1GHz最高可達49dBc,電路面積為0.81×0.64mm2。第四顆晶片改變累加器實現直接數位頻率合成器的工作頻率極限,使用CMOS 90 nm製程,工作頻率最高達5GHz,電路面積為0.98×1.34mm2 ,SFDR最高也可達49dBc。最後一顆晶片實作是利用translinear電路實現的直接數位頻率合成器,使用0.35um SiGe 製程,實驗結果電路可操作至5GHz,SFDR可達48.9 dBc。
In this thesis, we introduce the theorem of direct digital frequency synthesizer (DDFS) and the differences between the different DDFS structures, and then propose a new ROM-less DDFS using the method of Triangle-to-Sine Converter (TSC). In the proposed circuit, it not only combines the linear digital to analog converter which is often used in the convention ROM-base DDFS circuits, but also retains the advantage o from ROM-less DDFS ones. As a result, it is good at die area and power consumption than generally ROM-less DDFS. The TSC is the key point in proposed DDFS, thus we study and analyze the TSC in detail. There are five chips designed in this thesis. The first one is translinear circuits. The chip is implemented in 0.18um CMOS technology with the die area 0.51×0.58mm² and the power consumption is about 19mW. The second is the same circuit the first chip implemented which is in 0.35um SiGe technology with the die area 0.66×0.62mm² and the power consumption is about 37mW. The third chip is the DDFS in 0.18um CMOS technology with the die area 0.81×0.65mm². The measured result of operation speed is up to 2GHz,and the maximum of SFDR is 49 dBc with 1GHz speed. The four is for the ultra-high DDFS in 90nm CMOS technology with the die area 0.98×1.34mm². The operation speed is up to 5GHz, and the maximum SFDR is 49 dBc with 5GHz speed. In the last work, the DDFS is implemented in 0.35um SiGe technology. The operation speed is up to 5GHz, and the maximum SFDR is 49 dBc with 5GHz speed.
URI: http://hdl.handle.net/11455/6815
其他識別: U0005-2007201112110500
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2007201112110500
顯示於類別:電機工程學系所

文件中的檔案:
沒有與此文件相關的檔案。


在 DSpace 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。