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Low-power bus coding technologies for on-chip and off-chip bus connections
|引用:|| M.A. Elgamel and M.A. Bayoumi, “Interconnect noise analysis and optimization in deep submicron technology,” IEEE Circuits and Systems Magazine, vol. 3, no. 4, pp. 6-17, 2003.  K. Takeuchi, K. Yanagisawa, T. Sato, K. Sakamoto and S. Hojo, “Probabilistic crosstalk delay estimation for ASICs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 9, pp. 1377-1383, September 2004.  J. Cong, “An interconnect-centric design flow for nanometer technologies,” Proceedings of the IEEE, vol. 89. no. 4, pp. 505-528. April 2001.  R. Mita, G. Palumbo and M. Poli, “Propagation delay of an RC-chain with a ramp input,” IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 54, no. 1, pp. 66-70, January 2007.  P.P. Sotiriadis and A.P. Chandrakasan, “A bus energy model for deep submicron technology,” IEEE Trans. on Very Large Scale Integration Systems, vol. 10, no. 3, pp. 341-350, June 2002.  A. Vittal and M. Marek-Sadowska, “Crosstalk reduction for VLSI,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 3, pp. 290-298, March 1997.  M. Ghoneima, Y.I. Ismail, M.M. Khellah, J.W. Tschanz and V. De, “Formal derivation of optimal active shielding for low-power on-chip buses,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 821 - 836, May 2006.  H. Kaul, D. Sylvester and D. Blaauw, “Performance optimization of critical nets through active shielding,” Circuits and Systems I: Regular Papers, IEEE Trans. on Circuits and Systems, vol. 51, no. 12, pp. 2417-2435, December 2004.  L. Macchiarulo, E. Macii and M. Poncino, “Wire placement for crosstalk energy minimization in address buses,” Proceedings Design, Automation and Test in Europe Conference and Exhibition, 4-8, pp. 158-162, March 2002.  V. V. Deodhar and J.A. Davis, “Optimal voltage scaling, repeater insertion, and wire sizing for wave-pipelined global interconnects,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 55, no. 4, pp. 1023-1030, May 2008.  M.M. Ghoneima, M.M. Khellah, J. Tschanz, Ye Yibin, N. Kurd, J.S. Barkatullah, S. Nimmagadda, Y. Ismail and V.K. De, “Skewed repeater bus: a low-power scheme for on-chip buses,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 1904-1910, August 2008.  C.J. Akl and M.A. Bayoumi, “Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects,” Conference, Asia and South Pacific Design Automation, pp. 696-701, 2007.  E. Musoll, T. Lang and J. Cortadella, “Working-zone encoding for reducing the energy in microprocessor address buses,” IEEE Trans. Very Large Scale Integration Systems, vol. 6, no. 4, pp. 568-572, 1998.  Y. Aghaghiri, F. Fallah and M. Pedram, “ALBORZ: Address Level Bus Power Optimization,” Proceedings, International Symposium on Quality Electronic Design, pp. 470-475, 2002.  Youngsoo Shin, Kiyoung Choi and Young-Hoon Chang, “Narrow bus encoding for low-power DSP systems,” IEEE Trans. Very Large Scale Integration Systems, vol. 9, no. 5, pp. 656-660, 2001.  M. Madhu, V.S. Murty and V. Kamakoti, “Dynamic coding technique for low-power data bus,” Proceedings, IEEE Computer Society Annual Symposium on VLSI, pp. 252-253, 2003.  L. Macchiarulo, E. Macii and M. Poncino, “Low-energy encoding for deep-submicron address buses,” International Symposium on Low Power Electronics and Design, pp. 176-181, August 2001.  R.-B. Lin, “Inter-wire coupling reduction analysis of bus-invert coding,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 1911-1920, August 2008.  DDWG, Digital Visual Interface, V1.0, www.ddwg.org.  I. Choi, H. Shim and N. Chang, "Low-Power Color TFT LCD Display for Handheld Embedded Systems," ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 112-117, 2002.  K. Hirose and H. Yasuura, “A bus delay reduction technique considering crosstalk,” Proceeding Design, Automation and Test in Europe Conference and Exhibition, 27-30, pp. 441 - 445, March 2000.  S. W. Tu, Y. W. Chang and J. Y. Jou, “RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Page(s): 2258-2264, October 2006.  R. Ayoub and A. Orailoglu, “A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise and delay on processor buses,” Proceedings of the ASP-DAC Design Automation Conference, vol. 2, pp. 729 - 734, Jan. 2005.  Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang and TingTing Hwang, “A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 12, pp.2222-2227, Dec. 2007.  Jun So Pak, Jonghyun Cho, Joohee Kim, Junho Lee, Hyungdong Lee, Kunwoo Park and Joungho Kim, “TSV mutual inductance effect on impedance of 3D stacked on-chip PDN with Multi-TSV connections,” IEEE on CPMT Symposium Japan, pp. 1 - 4, 2010.  Guoqing Chen and E.G. Friedman, “Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis,” IEEE Trans. On Circuits and Systems II: Express Briefs, vol. 55, no. 1, pp. 26-30, 2008.  L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano, “Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems,” Proceedings Seventh Great Lakes Symposium on VLSI, pp. 77 - 82, 1997.  Y. Aghaghiri, F. Fallah and M. Pedram, “Irredundant address bus encoding for low power,” International Symposium on Low Power Electronics and Design, pp. 182-187, 2001.  W. Fornaciari, M. Polentarutti, D. Sciuto and C. Silvano, “Power optimization of system-level address buses based on software profiling,” Proceedings of the Eighth International Workshop on Hardware/Software Codesign, pp. 29-33, 2000.  S. Ramprasad, N. R. Shanbhag and I.N. Hajj, “A coding framework for low-power address and data busses,” IEEE Trans. Very Large Scale Integration Systems, vol. 7, no. 2, pp. 212-221, June 1999.  L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano, “Address bus encoding techniques for system-level power optimization,” Proceedings Design, Automation and Test in Europe, pp. 861-866, 1998.  C. G. Lyuh and T. Kim, “Low-power bus encoding with crosstalk delay elimination,” IEE Proceedings Computers and Digital Techniques, vol. 153, no. 2, pp. 93 - 100, March 2006.  Y. Zhang, J. Lach, K. Skadron and M.R. Stan, “Odd/even bus invert with two-phase transfer for buses with coupling,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 80-83, 2002.  K.-W. Kim,H.-B. Kwang, N. Shanbhag, C.L. Liu and S.-M. Kang, “Coupling-driven signal encoding scheme for low-power interface design,” IEEE/ACM International Conference on Computer Aided Design, 5-9, pp. 318-321, November 2000.  K. H. Baek, K. W. Kim and S. M. Kang; “A low energy encoding technique for reduction of coupling effects in SoC interconnects,” IEEE Midwest Symposium on Circuits and Systems, Proceedings of the 43rd, vol. 1, pp. 80 - 83, August 2000.  T. Lindkvist, J. Lofvenberg and O. Gustafsson, “Deep sub-micron bus invert coding,” Proceedings of the 6th Nordic Signal Processing Symposium, pp. 133-136, June 2004.  Z. Khan, T. Arslan and A.T. Erdogan, “Low power system on chip bus encoding scheme with crosstalk noise reduction capability,” IEE Proceedings Computers and Digital Techniques, vol. 153, no. 2, pp. 101 - 108, March 2006.  M. R. Stan and W. P. Burleson, “Bus-invert coding for low-power I/O,” IEEE Trans. on Very Large Scale Integration Systems, vol. 3, no. 1, pp. 49-58, March 1995.  Y. Shin, S. I. Chae and K. Choi, “Partial bus-invert coding for power optimization of application-specific systems,” IEEE Trans. on Very Large Scale Integration Systems, vol. 9, no. 2, pp. 377-383, April 2001.  C. Duan, A. Tirumala and S. P. Khatri, ”Analysis and avoidance of cross-talk in on-chip buses,” Hot Interconnects, Page(s): 133-138, August 2001.  S. Salerno, E. Macii and M. Poncino, “Energy-Efficient Bus Encoding for LCD Digital Display Interfaces,” IEEE Trans. on Consumer Electronics, vol. 51, no. 2, pp. 624-634, May 2005.  W. C. Cheng and M. Pedram, “Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface,” IEEE Trans. on Consumer Electronics, vol. 50, no. 1, pp. 320-328, February 2004.  Intel PXA250 and PXA210 Application Processors Developer's Manual, Intel, February 2002.  H. Parandeh-Afshar, A. Afzali-Kusha and A. Khakifirooz, “A very high performance address bus encoder,” Proceedings, IEEE International Symposium on Circuits and Systems, 2006.  C.J. Akl and M.A. Bayoumi, “Cost-effective and low-power memory address bus encodings,” IEEE International Symposium on Circuits and Systems, pp. 2010-2013, 2008.  H. Mehta, R.M. Owens and M.J. Irwin, “Some issues in gray code addressing,” Proceedings, Sixth Great Lakes Symposium on VLSI, pp. 178-181, 1996.  C. L. Su, C.Y. Tsui and A.M. Despain, “Saving power in the control path of embedded processors,” IEEE Design and Test of Computers 11, vol. 11, no. 4, pp. 24-31, 1994.  S. Komatsu and M. Fujita, “Low power and fault tolerant encoding methods for On-Chip Data transfer in practical Applications,” IEICE Trans. Very Large Scale Integration Systems, E88-A, pp. 3282-3289, 2005.  M. N. Mamidipaka, D.S. Hirschberg and N.D. Dutt, “Adaptive Low-Power Address Encoding Techniques Using Self-Organizing Lists,” IEEE Trans. Very Large Scale Integration Systems, vol. 11, no. 5, pp. 827-834, 2003.  Y. Aghaghiri, F. Fallah and M. PEdram, “EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses,” Proceedings, Design, Automation and Test in Europe Conference and Exhibition, 2002.  S. Komatsu and M. Fujita, “Irredundant address bus encoding techniques based on adaptive codebooks for low power,” Proceedings, Design Automation Conference, Asia and South Pacific of the ASP-DAC, pp. 9-14, 2003.  Performance Evaluation Laboratory, Brigham Young University (2000), http://traces.byu.edu/new/Documentation/.  Weste, N. H. E., and Harris, D., 2005, CMOS VLSI Design : A Circuits and Systems Perspective, Third Edition, Addison Wesley, USA.  G. S. Yee, R. Christopherson, T. Thorp, B. P. Wong and C. Schen, “An Automated Shielding Algorithm and Tool for Dynamic Circuits,” IEEE First International Symposium on Quality Electronic Design, pp. 369-374, 2000.  Y. Shin, S.-I. Chae and K. Choi, “Reduction of bus transitions with partial bus-invert coding,” Electronics Letters. vol. 34, no. 7, pp.642-643, April 1998.  B. Victor, and K. Keutzer, “Bus Encoding to Prevent Crosstalk Delay,” IEEE/ACM International Conference on Computer Aided Design, pp. 57-63, 2001.  J. Henker and H. Lekatsas, “A2BC: Adaptive Address Bus Coding for Low-Power Deep Sub-Micron Designs,” Proceedings of Design Automation Conference, pp.744-749, 2001.  M. Lajolo, “Bus Guardians: An Effective Solution for Online Detection and Correction of Faults Affecting System-on-Chip Buses,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 9, no. 6, pp. 974-982, 2001.  P. T. Huang and W. Hwang, “Low Power Encoding Schemes for Run-Time On-Chip Bus,” IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 2, pp. 1025-1028, 2004.  H. C. Yu and R. B. Lin, “Is More Redundancy Better for On-Chip Bus Encoding,” IEEE International Symposium on Circuits and Systems, pp. 2209-2212, 2006.  A. G. Weber, "USC-SIPI Image Database Version 5," USC-SIPI Report #315, October 1997, http://sipi.usc.edu/services/database/Database.html.|
最後我們以實驗去證實我們的論點，我們使用C語言去計算開關活動與耦合活動。然而，所有的匯流排編碼方法皆會增加一些額外的成本，例如: 電路面積，電路延遲，以及電路功率消耗。因此，我們使用 Hspice電路模擬工具，Design VisionTM 邏輯合成器以及SOC EncounterTM 實體層設計工具去估計電路面積，電路延遲，以及電路功率消耗。|
Since technology advances, the global interconnect power consumption and the delay of long wires are two of the most important key issues in nanometer technologies. In particular, both resistance and capacitive crosstalk effects between parallel wires result in serious problems such as crosstalk delay and power consumption. Furthermore, the crosstalk effects between parallel wires cause the power consumption and delay of on-chip buses worse than before. Thus, system designers must reduce the power consumption and delay of on-chip busses to improve the circuit performance in deep submicron (DSM) technologies. As display technology evolves, the standard of digital visual interface (DVI) 1.0 has replaced the conventional analog video graphics array (VGA) standard. However, the unit capacitance of LCD digital interface through a cable is up to 50pF/m for DVI and is also higher than that of PCB bus connections. The power dissipation is one of the most important key issues in LCD systems. Therefore, system designers also must reduce the power consumption to improve the LCD interface performance with the DVI standard. In this dissertation, we discuss two bus coding technologies: on-chip bus coding and off-chip DVI bus coding technologies. In order to reduce switching and coupling activities in on-chip instruction address busses, we propose a novel address bus coding technique, i.e. the XOR-BITS method. Address data on address busses are highly sequential, and the novel bus coding technique can reduce switching and coupling activities simultaneously. The realization of the bus codec requires a low-complex circuit and its delay is short after optimizations. In order to support the on-chip data bus coding, we propose two novel bus coding techniques, i.e. CDBI and ECDBI, to reduce the dynamic power dissipation and wire propagation delay. Data values on data busses are always random, and the novel bus coding techniques can reduce switching and coupling activities on busses simultaneously. The realizations of the CDBI and ECDBI methods only need low-complex architectures and the two methods also reduce redundant bus widths. However, coupling capacitances are several times larger than loading capacitances. Thus, we propose novel bus coding techniques to reduce crosstalk effects. The proposed bus coding methods reduce the dynamic power dissipation and wire propagation delay efficiently. They eliminate the worst crosstalk effect completely and reduce coupling capacitances largely. The novel bus coding techniques can also reduce switching and coupling activities simultaneously. Their realization architecture is low-complex, and the techniques also reduce redundant bus widths and eliminate the worst crosstalk effect. For the digital visual interface, we propose a new bus encoding technique, i.e. ADALP, to reduce the dynamic power dissipation on the interface efficiently. On the digital visual interface, digital images exhibit high correlation between adjacent pixels. The proposed encoding technique uses the absolute difference value and the codeword to reduce transition activities largely. Its realization architecture is low-complex and the DC balance is also considered. Finally, simulation results are shown to verify our bus coding techniques. We use C languages to model and calculate switching and coupling activities on busses. However, the proposed bus coding methods may require some overheads, including the area, delay and power of the bus codec circuits. Then we use Hspice circuit simulator, Design VisionTM logic synthesizer, and SOC EncounterTM physical design tool to estimate the area, delay, and power of the bus codec circuits.
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