Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6887
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dc.contributor謝明得zh_TW
dc.contributor邱瀝毅zh_TW
dc.contributor張孟凡zh_TW
dc.contributor林泓均zh_TW
dc.contributor張振豪zh_TW
dc.contributor.advisor范志鵬zh_TW
dc.contributor.author方嘉豪zh_TW
dc.contributor.authorFang, Chia-Haoen_US
dc.contributor.other中興大學zh_TW
dc.date2012zh_TW
dc.date.accessioned2014-06-06T06:39:08Z-
dc.date.available2014-06-06T06:39:08Z-
dc.identifierU0005-2106201114123900zh_TW
dc.identifier.citation[1] M.A. Elgamel and M.A. Bayoumi, “Interconnect noise analysis and optimization in deep submicron technology,” IEEE Circuits and Systems Magazine, vol. 3, no. 4, pp. 6-17, 2003. [2] K. Takeuchi, K. Yanagisawa, T. Sato, K. Sakamoto and S. Hojo, “Probabilistic crosstalk delay estimation for ASICs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 9, pp. 1377-1383, September 2004. [3] J. Cong, “An interconnect-centric design flow for nanometer technologies,” Proceedings of the IEEE, vol. 89. no. 4, pp. 505-528. April 2001. [4] R. Mita, G. Palumbo and M. Poli, “Propagation delay of an RC-chain with a ramp input,” IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 54, no. 1, pp. 66-70, January 2007. [5] P.P. Sotiriadis and A.P. Chandrakasan, “A bus energy model for deep submicron technology,” IEEE Trans. on Very Large Scale Integration Systems, vol. 10, no. 3, pp. 341-350, June 2002. [6] A. Vittal and M. Marek-Sadowska, “Crosstalk reduction for VLSI,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 3, pp. 290-298, March 1997. [7] M. Ghoneima, Y.I. Ismail, M.M. Khellah, J.W. Tschanz and V. De, “Formal derivation of optimal active shielding for low-power on-chip buses,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 821 - 836, May 2006. [8] H. Kaul, D. Sylvester and D. Blaauw, “Performance optimization of critical nets through active shielding,” Circuits and Systems I: Regular Papers, IEEE Trans. on Circuits and Systems, vol. 51, no. 12, pp. 2417-2435, December 2004. [9] L. Macchiarulo, E. Macii and M. Poncino, “Wire placement for crosstalk energy minimization in address buses,” Proceedings Design, Automation and Test in Europe Conference and Exhibition, 4-8, pp. 158-162, March 2002. [10] V. V. Deodhar and J.A. Davis, “Optimal voltage scaling, repeater insertion, and wire sizing for wave-pipelined global interconnects,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 55, no. 4, pp. 1023-1030, May 2008. [11] M.M. Ghoneima, M.M. Khellah, J. Tschanz, Ye Yibin, N. Kurd, J.S. Barkatullah, S. Nimmagadda, Y. Ismail and V.K. De, “Skewed repeater bus: a low-power scheme for on-chip buses,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 1904-1910, August 2008. [12] C.J. Akl and M.A. Bayoumi, “Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects,” Conference, Asia and South Pacific Design Automation, pp. 696-701, 2007. [13] E. Musoll, T. Lang and J. Cortadella, “Working-zone encoding for reducing the energy in microprocessor address buses,” IEEE Trans. Very Large Scale Integration Systems, vol. 6, no. 4, pp. 568-572, 1998. [14] Y. Aghaghiri, F. Fallah and M. Pedram, “ALBORZ: Address Level Bus Power Optimization,” Proceedings, International Symposium on Quality Electronic Design, pp. 470-475, 2002. [15] Youngsoo Shin, Kiyoung Choi and Young-Hoon Chang, “Narrow bus encoding for low-power DSP systems,” IEEE Trans. Very Large Scale Integration Systems, vol. 9, no. 5, pp. 656-660, 2001. [16] M. Madhu, V.S. Murty and V. Kamakoti, “Dynamic coding technique for low-power data bus,” Proceedings, IEEE Computer Society Annual Symposium on VLSI, pp. 252-253, 2003. [17] L. Macchiarulo, E. Macii and M. Poncino, “Low-energy encoding for deep-submicron address buses,” International Symposium on Low Power Electronics and Design, pp. 176-181, August 2001. [18] R.-B. Lin, “Inter-wire coupling reduction analysis of bus-invert coding,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 1911-1920, August 2008. [19] DDWG, Digital Visual Interface, V1.0, www.ddwg.org. [20] I. Choi, H. Shim and N. Chang, "Low-Power Color TFT LCD Display for Handheld Embedded Systems," ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 112-117, 2002. [21] K. Hirose and H. Yasuura, “A bus delay reduction technique considering crosstalk,” Proceeding Design, Automation and Test in Europe Conference and Exhibition, 27-30, pp. 441 - 445, March 2000. [22] S. W. Tu, Y. W. Chang and J. Y. Jou, “RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Page(s): 2258-2264, October 2006. [23] R. Ayoub and A. Orailoglu, “A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise and delay on processor buses,” Proceedings of the ASP-DAC Design Automation Conference, vol. 2, pp. 729 - 734, Jan. 2005. [24] Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang and TingTing Hwang, “A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 12, pp.2222-2227, Dec. 2007. [25] Jun So Pak, Jonghyun Cho, Joohee Kim, Junho Lee, Hyungdong Lee, Kunwoo Park and Joungho Kim, “TSV mutual inductance effect on impedance of 3D stacked on-chip PDN with Multi-TSV connections,” IEEE on CPMT Symposium Japan, pp. 1 - 4, 2010. [26] Guoqing Chen and E.G. Friedman, “Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis,” IEEE Trans. On Circuits and Systems II: Express Briefs, vol. 55, no. 1, pp. 26-30, 2008. [27] L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano, “Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems,” Proceedings Seventh Great Lakes Symposium on VLSI, pp. 77 - 82, 1997. [28] Y. Aghaghiri, F. Fallah and M. Pedram, “Irredundant address bus encoding for low power,” International Symposium on Low Power Electronics and Design, pp. 182-187, 2001. [29] W. Fornaciari, M. Polentarutti, D. Sciuto and C. Silvano, “Power optimization of system-level address buses based on software profiling,” Proceedings of the Eighth International Workshop on Hardware/Software Codesign, pp. 29-33, 2000. [30] S. Ramprasad, N. R. Shanbhag and I.N. Hajj, “A coding framework for low-power address and data busses,” IEEE Trans. Very Large Scale Integration Systems, vol. 7, no. 2, pp. 212-221, June 1999. [31] L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano, “Address bus encoding techniques for system-level power optimization,” Proceedings Design, Automation and Test in Europe, pp. 861-866, 1998. [32] C. G. Lyuh and T. Kim, “Low-power bus encoding with crosstalk delay elimination,” IEE Proceedings Computers and Digital Techniques, vol. 153, no. 2, pp. 93 - 100, March 2006. [33] Y. Zhang, J. Lach, K. Skadron and M.R. Stan, “Odd/even bus invert with two-phase transfer for buses with coupling,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 80-83, 2002. [34] K.-W. Kim,H.-B. Kwang, N. Shanbhag, C.L. Liu and S.-M. Kang, “Coupling-driven signal encoding scheme for low-power interface design,” IEEE/ACM International Conference on Computer Aided Design, 5-9, pp. 318-321, November 2000. [35] K. H. Baek, K. W. Kim and S. M. Kang; “A low energy encoding technique for reduction of coupling effects in SoC interconnects,” IEEE Midwest Symposium on Circuits and Systems, Proceedings of the 43rd, vol. 1, pp. 80 - 83, August 2000. [36] T. Lindkvist, J. Lofvenberg and O. Gustafsson, “Deep sub-micron bus invert coding,” Proceedings of the 6th Nordic Signal Processing Symposium, pp. 133-136, June 2004. [37] Z. Khan, T. Arslan and A.T. Erdogan, “Low power system on chip bus encoding scheme with crosstalk noise reduction capability,” IEE Proceedings Computers and Digital Techniques, vol. 153, no. 2, pp. 101 - 108, March 2006. [38] M. R. Stan and W. P. Burleson, “Bus-invert coding for low-power I/O,” IEEE Trans. on Very Large Scale Integration Systems, vol. 3, no. 1, pp. 49-58, March 1995. [39] Y. Shin, S. I. Chae and K. Choi, “Partial bus-invert coding for power optimization of application-specific systems,” IEEE Trans. on Very Large Scale Integration Systems, vol. 9, no. 2, pp. 377-383, April 2001. [40] C. Duan, A. Tirumala and S. P. Khatri, ”Analysis and avoidance of cross-talk in on-chip buses,” Hot Interconnects, Page(s): 133-138, August 2001. [41] S. Salerno, E. Macii and M. Poncino, “Energy-Efficient Bus Encoding for LCD Digital Display Interfaces,” IEEE Trans. on Consumer Electronics, vol. 51, no. 2, pp. 624-634, May 2005. [42] W. C. Cheng and M. Pedram, “Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface,” IEEE Trans. on Consumer Electronics, vol. 50, no. 1, pp. 320-328, February 2004. [43] Intel PXA250 and PXA210 Application Processors Developer's Manual, Intel, February 2002. [44] H. Parandeh-Afshar, A. Afzali-Kusha and A. Khakifirooz, “A very high performance address bus encoder,” Proceedings, IEEE International Symposium on Circuits and Systems, 2006. [45] C.J. Akl and M.A. Bayoumi, “Cost-effective and low-power memory address bus encodings,” IEEE International Symposium on Circuits and Systems, pp. 2010-2013, 2008. [46] H. Mehta, R.M. Owens and M.J. Irwin, “Some issues in gray code addressing,” Proceedings, Sixth Great Lakes Symposium on VLSI, pp. 178-181, 1996. [47] C. L. Su, C.Y. Tsui and A.M. Despain, “Saving power in the control path of embedded processors,” IEEE Design and Test of Computers 11, vol. 11, no. 4, pp. 24-31, 1994. [48] S. Komatsu and M. Fujita, “Low power and fault tolerant encoding methods for On-Chip Data transfer in practical Applications,” IEICE Trans. Very Large Scale Integration Systems, E88-A, pp. 3282-3289, 2005. [49] M. N. Mamidipaka, D.S. Hirschberg and N.D. Dutt, “Adaptive Low-Power Address Encoding Techniques Using Self-Organizing Lists,” IEEE Trans. Very Large Scale Integration Systems, vol. 11, no. 5, pp. 827-834, 2003. [50] Y. Aghaghiri, F. Fallah and M. PEdram, “EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses,” Proceedings, Design, Automation and Test in Europe Conference and Exhibition, 2002. [51] S. Komatsu and M. Fujita, “Irredundant address bus encoding techniques based on adaptive codebooks for low power,” Proceedings, Design Automation Conference, Asia and South Pacific of the ASP-DAC, pp. 9-14, 2003. [52] Performance Evaluation Laboratory, Brigham Young University (2000), http://traces.byu.edu/new/Documentation/. [53] Weste, N. H. E., and Harris, D., 2005, CMOS VLSI Design : A Circuits and Systems Perspective, Third Edition, Addison Wesley, USA. [54] G. S. Yee, R. Christopherson, T. Thorp, B. P. Wong and C. Schen, “An Automated Shielding Algorithm and Tool for Dynamic Circuits,” IEEE First International Symposium on Quality Electronic Design, pp. 369-374, 2000. [55] Y. Shin, S.-I. Chae and K. Choi, “Reduction of bus transitions with partial bus-invert coding,” Electronics Letters. vol. 34, no. 7, pp.642-643, April 1998. [56] B. Victor, and K. Keutzer, “Bus Encoding to Prevent Crosstalk Delay,” IEEE/ACM International Conference on Computer Aided Design, pp. 57-63, 2001. [57] J. Henker and H. Lekatsas, “A2BC: Adaptive Address Bus Coding for Low-Power Deep Sub-Micron Designs,” Proceedings of Design Automation Conference, pp.744-749, 2001. [58] M. Lajolo, “Bus Guardians: An Effective Solution for Online Detection and Correction of Faults Affecting System-on-Chip Buses,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 9, no. 6, pp. 974-982, 2001. [59] P. T. Huang and W. Hwang, “Low Power Encoding Schemes for Run-Time On-Chip Bus,” IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 2, pp. 1025-1028, 2004. [60] H. C. Yu and R. B. Lin, “Is More Redundancy Better for On-Chip Bus Encoding,” IEEE International Symposium on Circuits and Systems, pp. 2209-2212, 2006. [61] A. G. Weber, "USC-SIPI Image Database Version 5," USC-SIPI Report #315, October 1997, http://sipi.usc.edu/services/database/Database.html.zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/6887-
dc.description.abstract當製程演進至奈米世代,導線造成電路功率消耗與延遲,已經成為晶片設計中最重要問題之一。此外,導線間電阻與電容的耦合效應,也在電路上造成嚴重問題,例如串音。因此,在現今高速晶片匯流排之設計上,設計者必須面對比以往更加嚴重的耦合效應所造成之電路功率消耗與延遲。 另外,在顯示器演進發展中,數位視訊介面標準已經替換傳統類比視頻圖像陳列介面標準。然而,液晶顯示器訊號傳輸介面的單位電容高於印刷電路板匯流排電容,功率消耗也已經成為液晶顯示器介面訊號傳輸設計中最重要問題之一。因此,在現今數位視訊介面標準之設計上,設計者必須減少更多介面訊號傳輸的功率消耗。 在本論文中,我們針對匯流排編碼技術與數位視訊介面編碼技術做一系列詳細的探討與研究。首先,我們提出了新的位址匯流排編碼技術去有效減少在匯流排上的動態功率消耗。位址匯流排是屬於高循序模式,我們提出的位址匯流排編碼技術有幾項特徵,此位址匯流排編碼技術可同時減少開關活動及耦合活動,實作上只需低複雜度架構以及擁有最短的延遲路徑。 為了能夠支援不同的編碼模式,我們也提出了新的資料匯流排編碼技術去有效減少在匯流排上的動態功率消耗和傳遞延遲。資料匯流排是屬於隨機模式,我們提出的資料匯流排編碼技術有幾項特點,此資料匯流排編碼技術可同時減少開關活動及耦合活動,以及可縮減多餘的線寬,只需低複雜度的電路架構。然而,在奈米世代耦合電容遠大於負載電容。因此,我們針對耦合效應提出了新的資料匯流排編碼技術以有效減少在匯流排上的動態功率消耗和傳遞延遲。此提出的資料匯流排編碼技術可完全排除較嚴重的耦合效應,大大減少耦合電容,可同時減少開關活動及耦合活動,也可同時縮減多餘的線寬並且排除較嚴重的耦合效應,在實作上也只需低複雜度的電路架構。 針對數位視訊介面標準而言,我們也提出了新的編碼技術去有效減少在訊號傳輸介面上的動態功率消耗。因為鄰近的畫素是有高度相關性的,我們利用絕對差值與電書碼去進行傳輸介面的訊號編碼。使用我們提出的編碼技術,可減少開關活動並有效降低總功率消耗; 此編碼技術只需低複雜度的電路架構,並且可達到直流平衡。 最後我們以實驗去證實我們的論點,我們使用C語言去計算開關活動與耦合活動。然而,所有的匯流排編碼方法皆會增加一些額外的成本,例如: 電路面積,電路延遲,以及電路功率消耗。因此,我們使用 Hspice電路模擬工具,Design VisionTM 邏輯合成器以及SOC EncounterTM 實體層設計工具去估計電路面積,電路延遲,以及電路功率消耗。zh_TW
dc.description.abstractSince technology advances, the global interconnect power consumption and the delay of long wires are two of the most important key issues in nanometer technologies. In particular, both resistance and capacitive crosstalk effects between parallel wires result in serious problems such as crosstalk delay and power consumption. Furthermore, the crosstalk effects between parallel wires cause the power consumption and delay of on-chip buses worse than before. Thus, system designers must reduce the power consumption and delay of on-chip busses to improve the circuit performance in deep submicron (DSM) technologies. As display technology evolves, the standard of digital visual interface (DVI) 1.0 has replaced the conventional analog video graphics array (VGA) standard. However, the unit capacitance of LCD digital interface through a cable is up to 50pF/m for DVI and is also higher than that of PCB bus connections. The power dissipation is one of the most important key issues in LCD systems. Therefore, system designers also must reduce the power consumption to improve the LCD interface performance with the DVI standard. In this dissertation, we discuss two bus coding technologies: on-chip bus coding and off-chip DVI bus coding technologies. In order to reduce switching and coupling activities in on-chip instruction address busses, we propose a novel address bus coding technique, i.e. the XOR-BITS method. Address data on address busses are highly sequential, and the novel bus coding technique can reduce switching and coupling activities simultaneously. The realization of the bus codec requires a low-complex circuit and its delay is short after optimizations. In order to support the on-chip data bus coding, we propose two novel bus coding techniques, i.e. CDBI and ECDBI, to reduce the dynamic power dissipation and wire propagation delay. Data values on data busses are always random, and the novel bus coding techniques can reduce switching and coupling activities on busses simultaneously. The realizations of the CDBI and ECDBI methods only need low-complex architectures and the two methods also reduce redundant bus widths. However, coupling capacitances are several times larger than loading capacitances. Thus, we propose novel bus coding techniques to reduce crosstalk effects. The proposed bus coding methods reduce the dynamic power dissipation and wire propagation delay efficiently. They eliminate the worst crosstalk effect completely and reduce coupling capacitances largely. The novel bus coding techniques can also reduce switching and coupling activities simultaneously. Their realization architecture is low-complex, and the techniques also reduce redundant bus widths and eliminate the worst crosstalk effect. For the digital visual interface, we propose a new bus encoding technique, i.e. ADALP, to reduce the dynamic power dissipation on the interface efficiently. On the digital visual interface, digital images exhibit high correlation between adjacent pixels. The proposed encoding technique uses the absolute difference value and the codeword to reduce transition activities largely. Its realization architecture is low-complex and the DC balance is also considered. Finally, simulation results are shown to verify our bus coding techniques. We use C languages to model and calculate switching and coupling activities on busses. However, the proposed bus coding methods may require some overheads, including the area, delay and power of the bus codec circuits. Then we use Hspice circuit simulator, Design VisionTM logic synthesizer, and SOC EncounterTM physical design tool to estimate the area, delay, and power of the bus codec circuits.en_US
dc.description.tableofcontents1. Introduction…………………………………………………………………………..1 1.1 Background ……………………………………………………………………..1 1.2 Crosstalk Effects ……………………………………………………..…………3 1.3 Source of Power Consumption …………………………………………………7 1.4 Outline of This Thesis………………………………………………………...9 2. Review of Bus Coding Methods…………………………………………………….11 2.1 Basic Concepts………………………………………………………………..11 2.2 Bus Coding Methods for Address Busses ……………………….…………….12 2.2.1 T0 Coding Method……….……………………………………………….12 2.2.2 T0-C Coding Method……………………………………..……………...13 2.2.3 T0-xor Coding Method…………………………………….……………..14 2.2.4 INC-XOR Coding Method…………………………………………….....15 2.2.5 Dual_T0-BI Coding Method……………………………………………..15 2.3 Bus Coding Methods for Data Busses………………………………………...16 2.3.1 Bus-Invert Coding Method……………………………………………….16 2.3.2 Partial Bus-Invert Coding Method……………………………………….17 2.3.3 Odd/Even Bus-Invert Coding Method..………………….………………18 2.3.4 Coupling Bus-Invert Coding Method..………………..………………….20 2.3.5 Deep Sub-Micron Bus-Invert Coding Method…..…..………………….21 2.3.6 Khan Coding Method………….…………………..………….…………22 2.3.7 Duan Coding Method………..……………………..……………….……23 2.4 Bus Coding Methods for Digital Visual Interfaces……………………………24 2.4.1 Transition Minimized Differential Signaling Coding Method……….......25 2.4.2 Limited Intra-Word Transition Coding Method………………………...27 2.4.3 Chromatic Encoding Method…………………………………………….28 3. Efficient Low Power Coding Scheme for Address Busses………………………….30 3.1 Motivation…………………………………………………………………….30 3.2 Proposed Low Power Coding Scheme……………………………………….30 3.3 Experimental Results and Comparisons………………………………………35 3.3.1 Reduction in Switching Activity………………..……..…………………35 3.3.2 Reduction in Crosstalk………………………..………..…………………36 3.3.3 Reduction in Total Power Dissipation………..………..…………………38 3.4 Summary………………………………………………………………………41 4. Novel Low-Power Bus Invert Coding Methods with Crosstalk Detector…………..42 4.1 Motivation…………………………………………………………………….42 4.2 Crosstalk Detector Bus Invert Coding (CDBI) Method………………………42 4.3 Enhanced Crosstalk Detector Bus Invert Coding (ECDBI) Method………….46 4.4 Experimental Results and Comparisons………………………………………51 4.4.1 Results and Comparisons on Power Reduction…………………………..51 4.4.2 Results and Comparisons on Delay Reduction……….…………………..61 4.5 Summary…………………………………………………………………….62 5. Efficient RC Low-Power Bus Encoding Methods for Crosstalk Reduction………...64 5.1 Motivation……………………………………………………………………64 5.2 Proposed Method I…………………………………………………………….64 5.3 Proposed Method II…………………………………………………………..70 5.4 Experimental Results and Comparisons………………………………………73 5.4.1 Simulation Results on Crosstalk Reduction……………………….……..77 5.4.2 Simulation Results on Delay Reduction……………………………….…79 5.4.3 Simulation Results on Total Power Reduction…………….……………..80 5.5 Summary………………………………………………………………………88 6. Absolute Difference And Low-Power Bus Encoding Method for LCD Digital Display Interfaces……………………………………………………………………………….89 6.1 Motivation…………………………………………………………………….89 6.2 ADALP Encoding Method……………………………………………………90 6.3 Experimental Results and Comparisons………………………………………96 6.3.1 Comparisons of Simulation Results on Transition Activity Reduction…..97 6.3.2 Comparisons of Simulation Results on Total Power Reduction……..…...99 6.4 Summary……………………………………………………………………..101 7. Conclusions & Future works……………………………………………………….102 8. References………………………………………………………………………….106zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2106201114123900en_US
dc.subjectLow poweren_US
dc.subject低功耗zh_TW
dc.subjectbus encodingen_US
dc.subjectcrosstalk effectsen_US
dc.subject匯流排編碼zh_TW
dc.subject耦合效應zh_TW
dc.title應用於晶片匯流排連接之低功率匯流排編碼技術設計zh_TW
dc.titleLow-power bus coding technologies for on-chip and off-chip bus connectionsen_US
dc.typeThesis and Dissertationzh_TW
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