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|標題:||An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits|
|期刊/報告no：:||Ieee Transactions on Semiconductor Manufacturing, Volume 13, Issue 2, Page(s) 219-227.|
|摘要:||We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 mu m and wire thickness down to 0.15 mu m. The model is useful for VLSI design and process optimization.|
|Appears in Collections:||期刊論文|
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