Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6961
標題: 可應用於高階QAM調變系統之混合成本函數盲蔽式等化器設計與FPGA實作
FPGA Implementation and Design of A Fast Blind Equalization Algorithm with Novel Mixed Cost Function For High-Order QAM Systems
作者: 李偉
Lee, Wei
關鍵字: blind equalization algorithm
盲蔽式等化器
出版社: 電機工程學系所
引用: 1. 中文部分 [1]Ziemer,Tranter ,譯者:缪紹鋼 “通訊系統 Principles of Communications “ 5/e 高立圖書有限公司 [2] 鈦思科技股份有限公司,”視覺化建模環境 Simulink入門與進階” [3] http://www.terasoft.com.tw [4] http://www.dgt.gov.tw 2. 西文部分 [5] John G. Proakis, Digital Communications, Fourth edition, McGraw-Hill, 2001. [6] D. Godard, ”Self-Recovering Equalization and Carrier Tracking in Two-Dimensional Data Communication Systems”, IEEE Transactions on Communications, vol. 28, pp. 1867-1875, 1980. [7] Nam Oh, K. and Ohk Chin, Y, “New Blind Equalization Techniques Based on Constant Modulus Algorithm”, IEEE Conference Global Telecommunications, vol. 2, pp 865-869, 1995. [8] Ching-Hsiang Tseng and Cheng-Bin Lin, “A Stop-and-Go Dual-Mode Algorithm for Blind Equalization”, IEEE Conference Global Telecommunications, vol. 2, pp.1427-1431, 1996. [9] Weerackody V. and Saleem A. Kassam, “Dual-Mode Type Algorithms for Blind equalization”, IEEE Transactions on Communications, volume 42, pp.22-28, 1994. [10] Michael J. Ready and Richard P. Gooch, “Blind Equalization Based On Radius Directed Adaption”, IEEE International Conference Speech, and Signal Processing, vol. 3, pp.1699-1701, 1990. [11] S. Chen, “Low Complexity Concurrent Constant Modulus Algorithm and Soft Decision Directed Scheme for Blind Equalization”, IEE Proceedings Image and Signal Processing, vol. 150, pp.312-320, 2003. [12] S. Chen, S. McLaughlin, P.M. Grant and B. Mulgrew, “Multi-Stage Blind Clustering Equaliser”, IEEE Transactions on Communications, vol. 43, pp.701-705, 1995. [13] Giorgio Picchi and Gincarlo Prati, “Blind Equalization and Carrier Recovery Using a “Stop-and-Go” Decision-Directed Algorithm”, IEEE Transactions on Communications, vol. 35, pp.877-886, 1987. [14] Fernando C.C De Castro, Maria C. F. De Castro and Dalton S. Arantes, “Concurrent Blind Deconvolution for Channel Equalization”, IEEE International Conference Communications, vol. 2, pp.366-371, 2001. [15] H. N. King and Y. T. Lee and S.W. Kim, “Mathematical Modeling of VSB-Based Digital Television System”, ETRI Journal , vol. 25, no.1, pp.9-18, February 2003. [16] http://www.lartch.com. [17] http://www.xilinx.com
摘要: 在現代的通訊系統裡,數位通訊系統被應用的範圍越來越廣泛,如手持式電子裝置(如行動電話、PDA)、無線網路、數位電視系統等。數位通訊系統在傳輸訊號時有它不可避免的缺點,其中我們想深入研究是數位通訊系統在傳輸的過程中所遇到非理想的傳輸通道的問題。訊號在傳送的過程中,訊號會受到傳輸的距離、障礙物或傳送端與接收端之間有移動等等的因素,這樣非理想的多路徑通道會造成的傳輸訊號的干擾與失真。在數位通訊裡,用來消除多路徑通道效應的稱為等化器或者是通道估測。其目的在於估測出非理想多路徑通道的脈衝響應,藉以消除對於傳輸訊號的干擾與失真。 為了在不浪費頻寬的前提下,又能夠估計出通道響應,這類的等化器被稱為盲蔽式的等化器。這類的等化器不需要使用訓練符元,是依據所接收到訊號的特性處理,消除多路徑通道所造成的訊號干擾與失真。也因為不使用訓練符元所以盲蔽式的等化器在演算法的部分也就會比較複雜。另外一個要考量的部分是等化器硬體電路的實作;許多的盲蔽式等化器可能因為使用較大的運算量或者是較複雜的演算法,經過數學模型的驗證可以做到很優良的等化器性能,將失真的訊號很完美的修正回來,但是真正的使用硬體電路是沒有辦法將太複雜的演算法實現出來。所以在經過收集許多盲蔽式等化器相關的演算法裡,以及考量到演算法用硬體電路實現的可行性上,決定要使用適應性濾波器架構的等化器,而等化器的演算法則是要參考固定模數等化器演算法。 我們推導出一個複雜度不高,可以用硬體電路實作,相較於所比較的盲蔽式等化器具有更佳的收斂特性與收斂速度。而且可以把盲蔽式等化器應用到高階的QAM(64/256/1024)調變系統。首先在MATLAB中驗證演算法的正確性與效能,再與其他的相關演算法比較盲蔽式等化器的性能,根據驗證的結果證明演算法是可行的;接著就要將硬體架構實現,先利用SimulinkTM模組化建立等化器電路與SignalWAVeTM驗證平台的FPGA驗證。最後是用硬體描述語言,完成等化器的硬體電路,經由XilinxTM FPGA的電路合成,使得等化器電路在考慮到時脈與電路延遲下,能夠正確的動作,再FPGA 合成後電路所需的面積為7840,電路的速度為17.765ns,相當於56.3MHz。
The application range of digital communication systems is more and more larger in the modern communication systems, for instance, handheld electronic devices (PDA/mobile phone), wireless networks and digital television systems. However, there are many unavoidable drawbacks. Especially, we want to further study the filed which is the multi-path impairments of transmission channel effect for transmission signal. Digital signals are generated by some modulation methods and send to the receiver side. During the transmission of signals, signals will be distorted due to the distance and obstacles between the transmitter and the receiver, and the transmitter and receiver moves with the different velocity. These factors are named the multi-path impairments of transmission channel. The distortion of signals is named the inter-symbol interference. The different communication systems have their own multi-path channel. How to remove the multi-path channel effect is the important object. In digital communication systems, equalizers or channel estimations can overcome the multi-path impairments of transmission channel effect. Equalizers or channel estimations get inverse channel impulse response and remove the multi-path impairments of transmission channel effect. Blind equalization can save data bandwidth and accurately find the inverse channel impulse response. Blind equalization operates without training symbols by only using received symbol property to adjust equalize coefficients. However, bind equalization is more complexity than equalizations with training symbols. Another fact that we have to consider is the hardware implementation of blind equalization. Many blind equalization algorithms have the higher performances but they need very high computing complexity. In fact, the very complex algorithms can not be implemented by suitable digital logic circuits. Therefore, we refer many papers about blind equalizations and consider the corresponding hardware architecture. Then, we decide to apply the adaptive filter architecture and use the constant modulus blind equalization algorithm. We derive the new algorithm from modify constant modulus algorithm and the LMS-like algorithm. The proposed blind equalization has the lowest complexity and can be implemented by digital logic circuits. By comparing with the others CMA-based blind equalization algorithms, the proposed algorithm has better converge rate and performance than the existed methods, and can apply to the high-order QAM(64/256/1024) systems. First, we simulate the proposed algorithm with MATLAB software to prove the correctness and performance of the proposed algorithm, and compares with the others CMA-based blind algorithms. Then, the proposed algorithm actually has the highest equalization performance. Next, we implement the blind equalization at SimulinkTM environment and do FPGA emulation by the SignalWAVeTM board. Finally, through the XilinxTM FPGA place & route design flow, we can observe that the equalization circuits can run up to 56.3MHz (17.765ns).
URI: http://hdl.handle.net/11455/6961
其他識別: U0005-2606200623112100
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2606200623112100
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