Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7077
標題: 8位元200-MS/s之全差動管線式類比數位轉換器
A 8-BIT 200-MS/s FULLY DIFFERENTIAL PIPELINE A/D CONVERTER
作者: 張智翔
Yang, Ching-Yuan
出版社: 電機工程學系
摘要: 摘 要 類比數位轉換器在資料的取得方面是一個相當重要的角色,對於其8位元且高速的類比數位轉換器,尤其像是應用在儀器以及通訊方面的系統,己被廣泛應用。以一個數位式的示波器為例,它即是使用八位元數百MHz的類比數位轉換器,本篇論文的設計技巧,是針對於高速且低功率的CMOS管線數位類比轉換器而加以設計。 此8位元200MHz的雙通道管線式類比數位轉換器,實現於單一晶片上,其電路包含了取樣保持電路、1.5位元子類比數位轉換器、1位元數位類比轉換器、增益級、數位錯誤校正邏輯電路、及時序產生器電路等。電路是使用台積電TSMC 0.35μm 2P4M製程所設計。輸入電壓範圍為 ,電源電壓為3.3V。依據Hspice 模擬結果,整個管線式類比數位轉換器可操作在200MHz之取樣頻率,在9.96MHz之輸入頻率下,其訊號雜訊失真比為48.67dB,有效位元數為7.79位元,其消耗功率為212mW,整體電路佈局面積為(含PAD) 1.8mm1.8mm。
Abstract Analog-to-digital converters (ADC) play a crucial role in the design of data acquisition interfaces, particularly high-speed ADCs with resolutions of 8-bits find wide application in instrumentation and communication systems. For example, portable digital oscilloscopes use 8-bit ADCs with sampling rates above one hundred megahertz. This thesis describes design techniques for the high-speed and low-power CMOS pipeline A/D Converter. The two channels of a 8-bit 200MHz pipelined ADC is implemented in a single chip. The pipelined ADC consists of the building blocks like a sample-and-hold circuit, 1.5bit/stage sub-ADCs, 1bit DACs, gain stages, a digital error correction logic circuit and a clock generator. The circuit is implemented in TSMC 0.35μm 2P4M CMOS process. The input range of ADC is under 3.3V power supply. Accroding to Hspice simulation result, the designed pipelined ADC can operate at the sampling frequency of 200MHz. The Singal-to-Noise and Distortion Rate is 48dB when the input frequency is 10MHz and effective number of bit is 7.6bit. The power dissipation is 212mW. The chip area occurs 1.8mm1.8mm.
URI: http://hdl.handle.net/11455/7077
Appears in Collections:電機工程學系所

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