Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7245
標題: 系統晶片資料及位址匯流排編碼之低功率架構設計
Low Power Bus Coding Architecture for System-on-Chip Data and Address Busses
作者: 方嘉豪
Fang, Chia-Hao
關鍵字: low power
低功率
activity switching
address bus coding
data bus coding
動態活動開關
位址匯流排編碼法
資料匯流排編碼法
出版社: 電機工程學系
摘要: 摘要 低功率設計在現今的超大型積體電路(VLSI)中已成為舉足輕重的一個環節。由於匯流排通常消耗大量的功率,減少晶片功率消耗的有效方法是降低匯流排上的功率消耗。因此,匯流排編碼(bus coding)方法是利用匯流排資料特性來降低匯流排上資料轉換的次數(switching activity)以及在匯流排靜態電流的流失,因而達到低功率消耗的設計目的。 在積體電路中,主要的功率消耗包含有負載電容,活動開關,工作頻率以及供應電壓。每個工程師都必須依據上面幾點功率消耗的因素,解決在不同的設計階層關於功率消耗的問題其中包含有電路(circuit)層、架構(architecture)層、邏輯(gate)層等。基本上,功率消耗是與負載電容成比例關係。此外,外部匯流排(off-chip)上的負載電容約為內部匯流排(on-chip)的一千倍。相對地,每次開關活動(switching activity)的變化,在匯流排(off-chip)上的功率消耗約為內部匯流排(on-chip)的一千倍。假如有效地降低匯流排上的開關活動(switching activity)將能夠減少功率消耗。在這論文中,為了有效減少在匯流排上的開關活動,我們提出一種新的編碼技術。此外,它也可以節省動態功率的消耗。這編碼方法命名為XOR-BITS碼。這XOR-BITS碼可同時被運用在位址匯流排以及在資料匯流排上。它能在位址匯流排上減少74.16%的開關活動。同時,它也能在資料匯流排上減少13.65% 的開關活動。因此,這XOR-BITS碼不僅節省較多的功率消耗並且提升整體系統上的效能。 我們的編碼法與其他編碼法相互比較。XOR-BITS碼被證實比其他編碼法有較小的開關活動在資料匯流排以及位址匯流排上。此外, XOR-BITS碼的電路複雜度並不會與其他編碼法電路增加許多。我們使用MATLAB軟體去計算開關活動(switching activities)數。此外,我們也使用Modelsim 軟體驗證功能與Design Vision軟體去合成我們的設計,並且估計它的邏輯數與功率消耗。
In modern VLSI design, low power design is one of the key issues. Since on-chip and off-chip bus consume a general quantity of power, one of the effective methods to reduce the power consumption on chip is to reduce the power consumed by the on-chip and off-chip buses. Therefore, bus coding methods, that make capital of bus value characteristics to reduce the switching activity and static current loss on a bus, have been proposed to accomplish the objective. In integrated circuit, major sources for power dissipation include load capacitance, switching activity, work frequency and supply voltage. Based on the above power dissipation factors, every engineer has to solve power dissipation question in different design levels, including circuit level, architecture level, and gate level. The power dissipation, in the main, is in proportion to load capacitance. Moreover, the load capacitance from off-chip buses is about thousands of that from on-chip buses. Relatively, the power dissipation from off-chip buses is about thousands of that from on-chip buses. If we are effectively lowered the switching activity of the bus, we can reduce power dissipation significantly. In this thesis, the purpose of the proposed new coding technique is to effectively diminish the switching activity on the busses. In addition, it can save dynamic power consumption. The proposed encoding method is called the XOR-BITS code. The XOR-BITS coding can be used on address bus and it can also be applied on data bus simultaneously. It can reduce about 74% switching activity in the address bus. Meanwhile, it can also reduce switching activity in the data bus for about 14%. Consequently, the proposed XOR-BITS code can not only save more power consumption but also extend the whole system working time. Our bus coding method contrasts mutually with other bus coding method. The XOR-BITS coding is verified to achieve less switching activity than other coding methods on data bus and address bus. Besides, the increase of the circuit complexity is limited. We have used the MATLAB software to calculate the switching activities in behavior simulation. Furthermore, we have used the Design Vision software to synthesize our bus coder, and estimate the gate counts and power consumption.
URI: http://hdl.handle.net/11455/7245
Appears in Collections:電機工程學系所

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