Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7270
標題: 以相位補償技巧實現IEEE 802.11 a/b/g 通道的非整數-N頻率合成器
A Fractional-N Frequency Synthesizer with a Phase-Compensation Technique for IEEE 802.11 a/b/g Channels
作者: 陳建文
Chen, Jen-Wen
關鍵字: PLL
鎖相迴路
DLL
Frequency Synthesizer
延遲鎖相迴路
頻率合成器
出版社: 電機工程學系
摘要: 在組成一個完整無線通信系統的過程中,本地端頻率合成器所產生的振盪信號佔了一個很重要的部分。因為在晶片中無論哪裡需要時脈振盪訊號,頻率合成器都必須提供一個乾淨、穩定和可程式化的振盪信號。因此市面上幾乎所有的無線通信晶片皆是以鎖相迴路來當作頻率合成器。 要實現一個非整數N的頻率合成器,我們通常會利用補償的技巧來達到所需,然而這卻產生了一個問題,因為這種非整數N是利用整數除頻器的除率在2個整數之間來回跳動,利用平均的方法,達到除非整數N的目的,因此這種技巧會在迴路中造成相位誤差,雖然我們可以利用為雜訊展頻而應用在PLL中的超取樣 - 調變器技巧來降低相位誤差,但是這種數位的技巧,卻因為解析度的有限,而有量化的誤差。 為了解決上述的限制,因此在本論文中,我們發展出一種有別以往的架構,利用相位補償的技巧,相位誤差的問題便能再次的降低,而這個高速非整數N除頻器的工作範圍至少在3G Hz到4G Hz之間,並提供N + (f / 16)的除率,在此我們採用DLL來提供相位補償所需之相位,並經由實驗與量測來證實此架構之可行性。
To constitute a complete transceiver for modern wireless communication systems, the frequency synthesizer which generates the local oscillator (LO) signal is an indispensable building block. Wherever frequencies are translated, frequency synthesis is crucial to provide clean, stable and programmable LO signals. The phase-locked loop (PLL) is used for a frequency synthesizer in almost all wireless communication chipsets on the market. In order to implement a fractional-N frequency synthesizer, we need compensation techniques. However, it would cause problems when the division ratio of the frequency divider switches between two integers, it would increase the phase noise in a feedback network. Even if we can decrease it with noise shaping of PLL characteristic by using oversampling-modulator technique, it may still cause quantization error. In this thesis, we develop a new fractional-N frequency divider architecture to improve the above-mentioned limitation with the aid of a phase compensated technique. Because of the constant division ratio, the phase noise problem in frequency divider could be reduced. The new high-frequency fractional-N frequency divider with a phase compensation technique can be operated with input signal frequency ranging at least from 3G Hz to 4G Hz, and achieve the divide ratio of N + (f / 16). The on-chip phase compensation by a delay-locked loop (DLL) is adopted to reduce the fractional spurs in the fractional-N frequency synthesizer. The experiments prove the chip to work properly.
URI: http://hdl.handle.net/11455/7270
Appears in Collections:電機工程學系所

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