Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7329
標題: 適用於IEEE 802.11b/g 通道之三角積分調變非整數N頻率合成器
A Delta-Sigma Modulated Fractional-N Frequency Synthesizer for IEEE 802.11 b/g Channels
作者: 江奎儒
Jiang, Kuei-Zu
關鍵字: frequency synthesizer
頻率合成器
delta-sigma
fractional
三角積分
非整數
出版社: 電機工程學系
摘要: 本論文主要目標是配合射頻前端電路的架構設計一個具有高速、低功率損耗和低雜訊,且可以應用於IEEE 802.11 b/g 的通道的射頻頻率合成器。其中,壓控振盪器是使用電感電容共振的振盪器以達到低雜訊的特性;除率控制的部份為一個全數位的三角積分調變器來控制頻率合成器中的除頻器,使本電路可以有非整數的除率進而達到可以選擇通道的目標。並以鎖相迴路(phase-locked loop)理論為基礎,去探討非整數N頻率合成器的概念、架構、以及電路的實現。最後,我們以1.8V,0.18-um CMOS 製程來設計整個非整數N頻率合成器,其工作頻率為1.6GHz,消耗功率29.05mW。
The goal of this work is to design a high speed,low power consumption,and low noise RF frequency synthesizer.It can be applied to the RF front-end architecture of the IEEE 802.11 b/g channels.In this work,the VCO is an LC-tank oscillator to get the low noise performance,and an all digital delta-sigma modulator,which controls the divider of the synthesizer,is designed to present the channel selection and the fractional division ratio.Basing on the theory of phase-locked loop,the concepts,several different architectures,and the implementation of the fractional-N frequency synthesizer are given.The fractional-N frequency synthesizer is fabricated in a 1.8V,0.18-um CMOS technology,and consumes 29.05 mW in the operating frequency of 1.6 GHz.
URI: http://hdl.handle.net/11455/7329
Appears in Collections:電機工程學系所

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