Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7330
標題: 二階與多階非揮發性記憶體之感測與驗證相關電路設計
Bi-level and Multi-level Sensing/Verifying Related Circuit Design for Non-Volatile Memories
作者: 鍾秋嬌
Chung, Chiu-Chiao
關鍵字: Bi-level
二階
Multi-level
Sensing/Verifying Circuit
Non-Volatile Memories
Embedded
多階
非揮發性記憶體
感測與驗證電路
嵌入式
出版社: 電機工程學系所
引用: [1] E. C.-S. Yang, C.-J. Liu, T.-S. Chao, M.-C. Liaw, and C. C.-H. Hsu, “Novel Bi-directional Tunneling NOR (Bi-NOR) Type 3-D Flash Memory Cell,” Symp. on VLSI Technology Dig., pp. 85-86, 1999. [2] A. H.-F. Chou, E. C.-S. Yang, C.-J. Liu, H.-H. Pong, M.-C. Liaw, T.-S. Chao, Y.-C. King, H.-L. Huang, and C. C.-H. Hsu, “Comprehensive Study on a Novel Bi-directional Tunneling Program/Erase NOR-Type (Bi-NOR) 3-D Flash Memory Cell,” IEEE Trans. Electron Devices, Vol. 48, pp. 1386-1393, 2001. [3] S. Chang, E. C.-S. Yang, T. Chen, L. Huang, B. Hsu, D. Sung, J.-C. Duh, C.-W. Hung, V. Huang, Y.-C. King, C.-H. Chu, and C. C.-H. Hsu, “New Buried Bit-line NAND (Bi-NAND) Flash Memory for Data Storage,” VLSI Circuits Dig. Technical Papers, pp. 95-96, June 2003. [4] K.-H. Lee, and Y.-C. King, “New Single-Poly EEPROM with Cell Size down to 8F2 for High Density Embedded Nonvolatile Memory Applications,” Symp. on VLSI Technology Dig. Technical Papers, pp. 93-94, 2003. [5] K.-H. Lee, and Y.-C. King, “High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications,” Japanese Journal of Applied Physics, Vol. 44, No. 1A, pp. 44-49, 2005. [6] K.-H. Lee, M.-Y. Wu, S.-H. Dai, and Y.-C. King, “CMOS-Process-Based Ultra High Density Flash Memory Cell and Array Architecture,” Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, pp. 358-359, 2004. [7] M. Ohkawa et at. “A 9.8 mm2 Die Size 3.3 V 64 Mb Flash Memory with FN-NOR Type Four Level Cell,” IEEE J. Solid-State Circuits, Vol. 31, pp. 1584-15, Nov. 1996. [8] G. Campardo et at., “40-mm2 3-V Only 50-Mhz 64-Mb 2-bit/cell CHE NOR Flash Memory,” IEEE J. Solid-State Circuits, Vol. 35, pp. 1655-1667, Nov. 2000. [9] A. Pierin, S. Gregori, O. Khouri, R. Micheloni, and G. Torelli, “High-Speed Low-Power Sense Comparator for Multilevel Flash Memories,” in Proc. 7th Int. Conference Electronics, Circuits and Systems, Vol. II, pp. 759-762, Dec. 2000. [10] C.-C. Chung, H. Lin, Y.-M. Shen, and Y.-T. Lin, “A Multilevel Sensing and Program Verifying Scheme for Bi-NAND Flash Memories,” on IEEE Int. Symp. VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT), pp. 267 - 270, April 27-29, 2005. [11] A. Azarkan, A. van Staveren, and F. Fruett, “A Low-Noise Bandgap Reference Voltage Source with Curvature Correction,” Symp. on IEEE Iint. Circuits and Systems (ISCAS), Vol. 3, pp. 205-208, May 26-29, 2002. [12] X. Wang, C. Si, and X. Xu, “Curvature-Compensated CMOS Bandgap Reference with 1.8-V Operation,” on Conference of High Density Microsystem Design and Packaging and Component Failure Analysis (HDP'06), pp. 20-23, 2006. [13] R. Dehghani, S. M. Atarodi, “A New Low Voltage Precision CMOS Current Reference with No External Components,” IEEE Trans. on Circuits and Systems - II: Express Briefs, Vol. 50, Issue 12, pp. 928-932, Dec. 2003. [14] J-S Wang, and H-Y Lee, “A New Current-Mode Sense Amplifier for Low-Voltage Low-Power SRAM Design,” Proc. IEEE Int. ASIC Conference, pp. 163-167, Sep., 1998. [15] S-M Yoo, et al., “New Current-Mode Sense Amplifier for High Density DRAM and PIM Architectures,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Vol. 4, pp.938-941, May, 2001. [16] S. M. Wang and C. Y. Wu, “Full Current-Mode Techniques for High-Speed CMOS SRAMs,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Vol. 4, pp. 580-582, May, 2002. [17] H. Onoda, et al., “A Novel Cell Structure Suitable for a 3-V Operation Sector Erase Flash Memory,” IEDM Tech. Dig., pp. 599-602, Dec., 1992. [18] H. Kume, et al., “A 1.28 µm2 Contactless Memory Cell Technology for a 3 V Only 64M Bit EEPROM,” IEDM Tech. Dig., pp. 991-993, Dec., 1992. [19] C. Calligaro, P. Rolandi, N. Telecco, and G. Torelli, “A Current Mode Sense Amplifier for Low Voltage Non-Volatile Memories,” Innovative System in Silicon Conference, pp. 141-147, 1996. [20] A. Chrisanthopoulos, Y. Moisiadis, A. Varagis, Y. Tsiatouhas, and A. Arapoyanni, “A New Flash Memory Sense Amplifier in 0.18 µm CMOS Technology,” Proc. IEEE Int. Conf. Electronics, circuits, and Systems (ICECS), Vol. 2, pp. 941-944, Sep., 2001. [21] E. Seevinck, P.J. Van Beers, and H. Ontrop, “Current Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's,” IEEE J. Solid-State Circuits, Vol. 26, pp. 525-536, 1991. [22] K. Sasaki, et al., “A 7-ns 140 mW 1-Mb CMOS SRAM with Latched Sense Amplifier,” IEEE J. Solid-State Circuits, Vol. 27, pp. 1511-1518, 1992. [23] T. Seki, E. Itoh, C. Furukawa, et al., “A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier,” IEEE J. Solid-State Circuits, Vol. 28, pp. 478-483, 1993. [24] T. N. Blalock, and R. C. Jaeger, “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier,” IEEE J. Solid-State Circuits, Vol. 26, pp. 542-548, 1991. [25] F. Liang, C.-C. Chung, M.-C. Hsieh, H. Lin, Y.-T. Lin, “A Robust High-Speed Low-Power Sense Amplifier for Flash Memories,” Proceedings, The 14 th VLSI design/CAD Symposium, pp. 373-376, August 12-15, 2003. [26] H. Lin and F. Liang, “A High Speed Current-Mode Multi-Level Identifying Circuit for Flash Memories,” IEICE Trans. Electron., Vol. E86-C, No. 2, pp. 229-235, 2003. [27] A. Hajimiri, and R. Heald, “Design Issues in Cross-Coupled Inverter Sense Amplifier,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Vol. 2, pp. 149-152, 1998. [28] H. S. Kim, J. D. Choi, J. Kim, W. C. Shin, D. J. Kim, K. M. Mang, and S. T. Ahn, “Fast Parallel Programming of Multi-level NAND Flash Memory Cells Using the Booster-line Technology,” VLSI Circuits Dig. Tech. Papers, pp. 65-66, 1997. [29] A. Nozoe, H. Kotani, T. Tsujikawa, K. Yoshida, K. Furusawa, M. Kato, T. Nishimoto, H. Kume, H. Kurata, N. Miyamoto, S. Kubono, M. Kanamitsu, K. Koda, T. Nakayama, Y. Kouro, A. Hosogane, N. Ajika, and K. Kobayashi, “A 256Mb Multilevel Flash Memory with 2MB/s Program Rate for Mass Storage Applications,” IEEE J. Solid-State Circuits, Vol. 34, No. 11, pp. 1544-1550, Nov. 1999. [30] T. Tanaka, Y. Tanaka, H. Nakamura, K. Sakui, H. Oodaira, R. Shirota, K.Ohuchi, F. Masuoka, and H. Hara, “A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3V-Only NAND Flash Memory,” IEEE J. Solid-State Circuits, Vol. 29, No. 11, pp. 1366-1373, Nov. 1994. [31] H. Kurata, N. Kobayashi, K. Kimura, and S. Saeki, “A Selective Verify Scheme for Achieving a 5-MB/s Program Rate in 3-bit/cell Flash Memories,” VLSI Circuits Dig. Tech. Papers, pp. 166-167, June 2000. [32] H. Nobukata, S. Takagi, K. Hiraga, T. Ohgishi, M. Miyashita, K. Kamimura, S. Hiramatsu, K. Sakai, T. Ishida, H. Arakawa, M. Itoh, I. Naiki, and M. Noda, “A 144-Mb, Eight-Level NAND Flash Memory with Optimized Pulsewidth Programming,” IEEE J. Solid-State Circuits, Vol. 35, No. 5, pp. 682-690, May 2000. [33] M. Bauer, R. Alexis, G. Atwood, B. Baltar, A. Fazio, K. Frary, et al., “A Multilevel-Cell 32Mb Flash Memory,” IEEE ISSCC Dig. Tech. Papers, Vol. 38, pp. 132-133, Feb. 1995. [34] K. Takeuchi, T. Tanaka, T. Tanzawa, “A Multi-Page Cell Architecture for High-Speed Programming Multi-Level NAND Flash Memories,” VLSI circuits Dig. Tech. Papers, pp. 67-68, June 1997. [35] J. M. Daga, C. Papaix, M. Merandat, S. Ricard, G. Medulla, and J. Guichaoua, “Design Techniques for EEPROMs Embedded in Portable System on Chips,” IEEE Design and Test of Computers, pp. 68-75, 2003. [36] R. Micheloni, L. Crippa, M. Sangalli, and G. Campardo, “The Flash Memory Read Path: Building Blocks and Critical Aspects,” Proceedings of IEEE, Vol. 91, No. 4, pp. 537-553, 2003. [37] G. Campardo, R. Micheloni, D. Novosel, VLSI-Design of Non-Volatile Memories, Berlin Heidelberg, Heidelberg: Springer-Verlag, 2005, Ch. 5. [38] http://www.cic.org.tw/~ate/index.htm, National Chip Implementation Center of National Applied Research Laboratories, 2004. [39] C.-H. Chen, “Design of Low-Power Embedded Non-volatile Memory System and Control Signal Generator,” Master thesis, Department of Electrical Engineering in National Chung-Hsin University, Tai-Chung, R.O.C., July 2006.
摘要: 快閃記憶體技術在近幾年中快速發展,雙向通道F-N 穿隧式NOR (Bi-NOR) 型與位元線埋入式NAND (Bi-NAND) 型的記憶體相繼開發問世,其目的在於提高記憶體的可靠度、提昇操作速度與降低操作電壓。針對Bi-NOR與Bi-NAND型快閃記憶體,本論文使用0.35-微米CMOS製程設計一套「交叉偶合式」的感測放大器,以改善傳統感測電路常發生的錯配效應、感測速度慢與高功率消耗等問題。 本論文也對前述非揮發性記憶體提出一系列「雙階與多階的感測與驗證」的電路設計。運用提出的感測放大器,發展一個簡捷二分式的感測與驗證技術,可以有效的減少「多階式非揮發性記憶體」在讀取與驗證實的循環次數與時間。 此外,針對文獻曾提出EEPROM元件所具備的低電壓、小尺寸與CHH寫入/CHE抹除技術的特性,本論文亦發展一套在0.35-微米CMOS製程下與「雙階式」EEPROM記憶元件共組的嵌入式電路系統。系統的週邊電路包括:位址緩衝器、列位址解碼器、電壓切換器、電壓驅動器以及感測與驗證電路等,配合適當的控制訊號即能完成對選取記憶元件的資料讀取、資料寫入與抹除的功能。其中驗證電路可針對欲寫入的資料內容做事先的檢查,並在寫入動作之後進行驗證的程序。這套電路系統只需擴增記憶體陣列與週邊電路,即可達到較高容量的應用。
In the recent flash memory technology, the Bi-directional channel tunneling NOR (Bi-NOR) and the Buried-bit-line NAND (Bi-NAND) memories were proposed for the purposes of high reliability, high speed, and low power operation. To improve the immunity of mismatch and speed up the sensing time without sacrificing the power consumption for Bi-NOR and Bi-NAND flash memories, a cross-coupled sense amplifier was implemented by using 0.35-um CMOS technology. A series of circuit designs involved in bi-level and multi-level sensing/verifying for non-volatile memories are presented in this dissertation. Based on the proposed sense amplifier, a compact dichotomous sensing/verifying technique was developed to reduce the cycle time of reading and verifying for multi-level flash memories. Furthermore, due to a low-voltage scaled-down EEPROM cell with CHH program/CHE erase technique was presented, a circuitry embedded with one-bit per cell bi-level EEPROM cell array in 0.35-um CMOS standard technology was also developed in this dissertation. The peripheral circuits, including address buffers, row decoders, voltage switches, voltage drivers, and sensing/verifying circuits, composed with the appropriate control signals, can perform operations not only in reading data, but also programming and erasing the addressed cells. The verifying circuit was developed for checking data to be programmed first, and then verifying the programmed results. This circuitry can be easily expanded for higher capacity by increasing the cell array and peripherals.
URI: http://hdl.handle.net/11455/7330
其他識別: U0005-0208200723484500
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0208200723484500
Appears in Collections:電機工程學系所

文件中的檔案:

取得全文請前往華藝線上圖書館



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.